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7.2.12 DDC Checksum Generator

B0129-01

Checksum

Generator

ChecksumRead-Only

ResultsUpdatedon

EachSyncEvent

InitializedOnSyncEventto “0000000000000010”

rxout_X_d

rxout_X_c

rxout_X_b

rxout_X_a

rxout_X_b

rxout_X_c

rxout_X_d

rxclk

sync

Results

AFE8405

14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER

www.ti.com

SLWS212 – OCTOBER 2008

PROGRAMMING

VARIABLE

DESCRIPTION

par_recv_fsinvl(6:0)

rx_sync_out (frame strobe) sync interval. 0 is 1 rxclk cycle and 127 is 128 rxclk cycles.

par_recv_clkdiv(6:0)

rxclk_out cycles per IQ channel sample; 1 is full rate, 2 is rxclk/2, etc.

par_recv_chan(3:0)

Number channels to be output. 0 is 1 channel, and 15 is 16 channels.

par_recv_sync_del(6:0)

Delays the DDC0 pser sync source to establish the timing of IQ DDC0. Increasing the value delays the

par_sync_out location.

par_recv_syncout_del(3:0)

Delays the rx_sync_out position with respect to IQ DDC0. Setting to 0 moves the rx_sync_out pulse one

rxclk_out cycle before the IQ DDC0 word, setting to 1 places it as shown above, lined up with IQ DDC0,

etc.

par_recv_rxclk_pol

rxclk_out polarity. Outputs data on falling edges when cleared, rising edges when set.

par_recv_sync_pol

Parallel interface par_sync_out polarity. 0 is active-low, 1 for active-high

par_recv_ena

Parallel TCI110 style interface enabled when set, serial interface enabled when cleared.

ssel_serial(2:0)

DDC channel serial interface sync source selection. All DDCs should be programmed to the same sync

source when using this parallel output interface.

gain_mon

When set, the parallel output data includes 8b I at I(15:8), 8b Q at Q(15:8), 14b AGC gain at I(7:0) and

Q(7:2) and 2b AGC state at Q(1:0).

3-state(6:3)

3-state controls for the rx_sync_out_X and rxout_X_X pins. Pins are in the high-impedance state when

the 3-state register bits are set.

The checksum generator is used in conjunction with the input test signal generator to implement a self-test

capability.

Figure 7-34. DDC Checksum Generator Block Diagram

The sync for the checksum generator is internally connected to the ddc_counter output.

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