AFE8405 datasheet(9/152 Pages) TI

9 / 152 page

3.8 DIGITAL CHIP AC TIMING CHARACTERISTICS

(1)

AFE8405

14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER

www.ti.com

SLWS212 – OCTOBER 2008

TA = –40°C to 85°C (unless otherwise noted)

PARAMETER

MIN

TYP MAX

UNIT

fCK

Clock frequency (adcclk_a/b/c/d, rxclk)(2)

160

MHz

tCKL

Clock low period (below VIL) (adcclk_a/b/c/d, rxclk)

(2)

tCKH

Clock high period (above VIH) (adcclk_a/b/c/d, rxclk)

(2)

tRF

Clock rise and fall times (VIL to VIH) (adcclk_a/b/c/d, rxclk)

(3)

Input setup (rx_sync[a–d]) before rxclk rises(2)

tSU

Input setup (rxin_a/b/c/d_[0-15] ) before rxclk rises (ADC FIFO blocks bypassed)(2)

Input setup (rxin_a/b/c/d_[0-15] ) before adcclk_a/b/c/d rises (ADC FIFO blocks enabled)(2)

Input hold (rx_sync[a–d]) after rxclk rises(2)

tHD

Input hold (rxin_a/b/c/d_[0-15] ) after rxclk rises (adc fifo blocks bypassed)(2)

2.5

Input hold (rxin_ a/b/c/d_[0-15] ) after adcclk_a/b/c/d rises (adc fifo blocks enabled)(2)

Data output delay (rx_sync_out_[0-7], rxout_[0-7]_a/b/c/d, rxclk_out, rx_sync_out,

tDLY

dvga_[a-d]_[5-0]) after rxclk rises.(2)

Data output hold (rx_sync_out_[0-7], rxout_[0-7]_a/b/c/d, rxclk_out, rx_sync_out,

tOHD

0.5

dvga_[a-d]_[5-0]) after rxclk rises.(2)

fJCK

JTAG clock frequency (tck)(2)

MHz

tJCKL

JTAG clock low period (below VIL) (tck)

(2)

tJCKH

JTAG clock high period (above VIH) (tck)

(2)

tJSU

JTAG input (tdi or tms) setup before tck goes high(2)

tJHD

JTAG input (tdi or tms) hold time after tck goes high(2)

tJDLY

JTAG output (tdo) delay from falling edge of tck.(2)

Control setup during reads or writes

tCSU

3 pin mode: a[5:0] valid before rd_n, wr_n or ce_n falling edge

2 pin mode: a[5:0] and wr_n valid before ce_n falling edge (2)

Control setup during writes

tEWCSU

3 pin mode: d[15:0] valid before wr_n and ce_n rising edge

2 pin mode: d[15:0] valid before ce_n rising edge (2)

Control hold during writes.

tCHD

3 pin mode: a[5:0] and d[15:0] valid after wr_n and ce_n rise

2 pin mode: a[5:0], d[15:0] and wr_n valid after ce_n rise (2)

tCSPW

Control strobe (ce_n and wr_n low) pulse duration during write. (2)

tCDLY

Control output delay ce_n and rd_n low and a[5:0] stable to d[15:0] during read. (2)

tREC

Control recovery time between reads or writes. (2)

tHIZ

Control end of read to Hi-Z. rd_n and ce_n rise to d[15:0] 3-state (4)

tCOH

Control read d[15:0] output hold time

(1)

Timing is measured from the respective clock at VDDS/2 to input or output at VDDS/2. Output loading is a 50-

Ω transmission line whose

delay is calibrated out.

(2)

Each part is tested at 90

°C case temperature for the given specification. Lots are sample tested at –40°C.

(3)

Recommended practice

(4)

Controlled by design and process and not directly tested.

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