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AFE8405 Datasheet(PDF) 79 Page - Texas Instruments |
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AFE8405 Datasheet(HTML) 79 Page - Texas Instruments |
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79 / 152 page  AFE8405 14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER www.ti.com SLWS212 – OCTOBER 2008 Page Register Address Registers Addressed With 5-Bit Address Space, Pins (a4:a0) Contents in Hex Pin a5 0x08E0 0 DDC4 CFIR taps 32 through 63 coefficient msbs (17:2) 0x0900 0 DDC4 control registers 0x00 through 0x1F 0x0920 0 DDC4 control registers 0x20 through 0x3F 0x0A00 0 DDC5 PFIR taps 0 through 31 coefficient lsbs (1:0) 0x0A20 0 DDC5 PFIR taps 32 through 63 coefficient lsbs (1:0) 0x0A40 0 DDC5 PFIR taps 0 through 31 coefficient msbs (17:2) 0x0A60 0 DDC5 PFIR taps 32 through 63 coefficient msbs (17:2) 0x0A80 0 DDC5 CFIR taps 0 through 31 coefficient lsbs (1:0) 0x0AA0 0 DDC5 CFIR taps 32 through 63 coefficient lsbs (1:0) 0x0AC0 0 DDC5 CFIR taps 0 through 31 coefficient msbs (17:2) 0x0AE0 0 DDC5 CFIR taps 32 through 63 coefficient msbs (17:2) 0x0B00 0 DDC5 control registers 0x00 through 0x1F 0x0B20 0 DDC5 control registers 0x20 through 0x3F 0x0C00 0 DDC6 PFIR taps 0 through 31 coefficient lsbs (1:0) 0x0C20 0 DDC6 PFIR taps 32 through 63 coefficient lsbs (1:0) 0x0C40 0 DDC6 PFIR taps 0 through 31 coefficient msbs (17:2) 0x0C60 0 DDC6 PFIR taps 32 through 63 coefficient msbs (17:2) 0x0C80 0 DDC6 CFIR taps 0 through 31 coefficient lsbs (1:0) 0x0CA0 0 DDC6 CFIR taps 32 through 63 coefficient lsbs (1:0) 0x0CC0 0 DDC6 CFIR taps 0 through 31 coefficient msbs (17:2) 0x0CE0 0 DDC6 CFIR taps 32 through 63 coefficient msbs (17:2) 0x0D00 0 DDC6 control registers 0x00 through 0x1F 0x0D20 0 DDC6 control registers 0x20 through 0x3F 0x0E00 0 DDC7 PFIR taps 0 through 31 coefficient lsbs (1:0) 0x0E20 0 DDC7 PFIR taps 32 through 63 coefficient lsbs (1:0) 0x0E40 0 DDC7 PFIR taps 0 through 31 coefficient msbs (17:2) 0x0E60 0 DDC7 PFIR taps 32 through 63 coefficient msbs (17:2) 0x0E80 0 DDC7 CFIR taps 0 through 31 coefficient lsbs (1:0) 0x0EA0 0 DDC7 CFIR taps 32 through 63 coefficient lsbs (1:0) 0x0EC0 0 DDC7 CFIR taps 0 through 31 coefficient msbs (17:2) 0x0EE0 0 DDC7 CFIR taps 32 through 63 coefficient msbs (17:2) 0x0F00 0 DDC7 control registers 0x00 through 0x1F 0x0F20 0 DDC7 control registers 0x20 through 0x3F 0x1000 0 Receive input AGC0 error RAM addresses 0 through 31 0x1020 0 Receive input AGC0 error RAM addresses 32 through 63 0x1040 0 Receive input AGC0 DVGA RAM addresses 0 through 31 0x1080 0 Receive input AGC0 gain RAM addresses 0 through 31 0x10A0 0 Receive input AGC0 gain RAM addresses 32 through 63 0x1100 0 Receive input AGC1 error RAM addresses 0 through 31 0x1120 0 Receive input AGC1 error RAM addresses 32 through 63 0x1140 0 Receive input AGC1 DVGA RAM addresses 0 through 31 0x1180 0 Receive input AGC1 gain RAM addresses 0 through 31 0x11A0 0 Receive input AGC1 gain RAM addresses 32 through 63 0x1400 0 Receive input AGC2 error RAM addresses 0 through 31 0x1420 0 Receive input AGC2 error RAM addresses 32 through 63 0x1440 0 Receive input AGC2 DVGA RAM addresses 0 through 31 Submit Documentation Feedback AFE8405 GENERAL CONTROL 79 |
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