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AFE8405 Datasheet(PDF) 30 Page - Texas Instruments |
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AFE8405 Datasheet(HTML) 30 Page - Texas Instruments |
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30 / 152 page  7 RECEIVE DIGITAL SIGNAL PROCESSING 7.1 Receive Input Interface B0106-01 FIFO 16 rxin_a (1) 16 DualRealor SingleComplex PowerMeter DualRealor SingleComplex AGC DualRealor SingleComplex AGC DualRealor SingleComplex PowerMeter FIFO 16 rxin_b (2) 16 FIFO 16 rxin_c 16 FIFO 16 rxin_d 16 dvga_c dvga_d dvga_a dvga_b 6 6 6 6 18 rx_distribution BustoDDC Channels Test&Noise Signal Generator Test&Noise Signal Generator Test&Noise Signal Generator Test&Noise Signal Generator 16 16 16 16 To Testbus TestBusSelect andDecimation Testbus Sources 1to64 Sample Delay Line 1to64 Sample Delay Line 1to64 Sample Delay Line 1to64 Sample Delay Line delay_a 18 delay_b 18 delay_c 18 delay_d AFE8405 14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER SLWS212 – OCTOBER 2008 www.ti.com The downconversion section of the AFE8405 consists of the receive input interface, the rx_distribution bus, and eight digital downconverter blocks. The purpose of the receive input interface is to accept signal data from three 16-bit input ports, measure the input signal power, control the digital VGA, and distribute the data to the DDC blocks. The input interface also has a user-controlled test generator and noise source. The rx_distribution bus distributes the three channels of signal data to each of the eight DDC blocks. Each DDC block selects one of the three channels (or two for complex input data) from the rx_distribution bus and then performs downconversion tuning, programmable delay, channel filtering with decimation, power measurement, fixed gain adjust, and/or automatic gain control. Each DDC block can support one UMTS channel, two CDMA channels, or two TD-SCDMA channels. An optional mode permits stacking two DDC blocks in UMTS mode to provide double-length final pulse-shape filtering. Tuned, filtered, and decimated signal data is output in bit-serial or parallel format. (1) Hard-wired to internal ADCA (2) The rxin_b port is not used and not connected internally. Figure 7-1. Receive Data Input Interface The AFE8405 receive input data interface accepts data from several sources: • Signal data from the integrated 14-bit ADC (rxin_a) • Signal data presented at the two 16-bit digital data input ports (rxin_c and rxin_d) • An LFSR test signal generator allows the AFE8405 to be tested using a known repetitive data sequence. RECEIVE DIGITAL SIGNAL PROCESSING 30 Submit Documentation Feedback |
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