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AFE8405 Datasheet(PDF) 33 Page - Texas Instruments

Part # AFE8405
Description  14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
PDF  152 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AFE8405 Datasheet(HTML) 33 Page - Texas Instruments

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B0108-01
21-Bit
Integration
Counter
Clear
58-Bit
Integrator
58-Bit
Register
9-Bit
SyncDelay
Counter
21-Bit
Interval
Counter
Transfer
Sync
Delay
(in8Sample
Increments)
Integration
(in8Sample
Increments)
21
21
9
RMSPower
I
Q
33
32
16
Interval
(in8Sample
Increments)
16
32
Interrupt
T0116-01
Sync
Delay
Sync
Event
Integration Time
Integration Time
Integration Time
Interval Time
Interrupt
Interrupt
Interrupt
Interval Time
Integration
Start
Integration
Start
Integration
Start
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
www.ti.com
SLWS212 – OCTOBER 2008
Figure 7-3. Detailed Functionality of Receive Input Power Meter
Figure 7-4. Receive Input Power Meter Timing
Power is calculated by squaring each 16-bit I (I and Q for complex inputs) sample, summing, and then
integrating the summed-squared results into a 58-bit accumulator over a programmable integration period.
The integration period is programmed into the 21-bit counter, in eight-sample increments. The power read
is:
Power = [ (I2)
× (N × 8 + 1) ] for real inputs, where N is the integration count.
Power = [ (I2 + Q2)
× (N × 8 + 1) ] for complex inputs, where N is the integration count.
A programmable 21-bit interval counter sets the power measurement interval (how often power is
measured) in eight-sample increments. A measurement integration period is started at the beginning of
each interval period.
The process begins with a sync event starting the 9-bit delay counter. After (8
× sync_delay + 2) samples,
the integration interval is started. Integration continues until the integration count is met, at which point the
58-bit integrator results are transferred to the read-only register and an interrupt is generated. A new
measurement period starts at the end of the interval period.
The 21-bit counters in eight-sample increments allow up to 104.8-mS interval times at 160-MHz clock.
Submit Documentation Feedback
RECEIVE DIGITAL SIGNAL PROCESSING
33



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