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AFE8405 Datasheet(PDF) 83 Page - Texas Instruments |
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AFE8405 Datasheet(HTML) 83 Page - Texas Instruments |
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83 / 152 page ![]() 8.4.2.2 PAGE Register AFE8405 14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER www.ti.com SLWS212 – OCTOBER 2008 Register name: PAGE Address: 0x01 BIT 15 BIT 8 Unused Unused Unused W(2:0) X Y(2) 0 0 0 0 0 0 0 0 BIT 7 BIT 0 Y(1) Y(0) Zp Unused Unused Unused Unused Unused 0 0 0 0 0 0 0 0 W(2:0): Selects which dual-DDC block to address. X: The DDC modules are configured as dual DDCs; an even-numbered DDC and odd-numbered DDC are contained in each dual-DDC module, the X bit selects which DDC gets address. (DDC0/2/4/6=0, DDC1/3/5/7=1) W(2:0) X bit Selected Block 000 0 DDC0 000 1 DDC1 001 0 DDC2 001 1 DDC3 010 0 DDC4 010 1 DDC5 011 0 DDC6 011 1 DDC7 100 0 Receive AGC0/1 RAMs 101 0 Receive AGC2/3 RAMs 110 0 Receive input interface Y(2:0): Within each major block, there are up to 8 different zones that can be addressed using the Y bits. Y(2:0) DDC Zone Receive Input Interface Zone Receive AGC RAMs Zone 000 PFIR coeffient lower 2 bits CHIPS control registers RAGC0/2 ERRMAP 001 PFIR coeffient upper 16 bits RAGC control registers RAGC0/2 DVGAMAP 010 CFIR coeffient lower 2 bits Not assigned RAGC0/2 GAINMAP 011 CFIR coeffient upper 16 bits Not assigned Not assigned 100 Control registers Not assigned RAGC1/3 ERRMAP 101 Not assigned Not assigned RAGC1/3 DVGAMAP 110 Not assigned Not assigned RAGC1/3 GAINMAP 111 Not assigned Not assigned Not assigned Zp: The Zp bit is the MSB of the address word sent to the registers and RAMs. This bit can be thought of as an upper/lower selector of the 64-word addressing. Submit Documentation Feedback AFE8405 GENERAL CONTROL 83 |
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