AFE8405 datasheet(46/152 Pages) TI

46 / 152 page

7.2.2

DDC Mixer

B0119-01

4to2

Select

Demux

and

Round

Sin

Cos

FromNCO

mixer_gain

From

rx_distribution

Bus

Channel

Delay

AFE8405

14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER

SLWS212 – OCTOBER 2008

www.ti.com

Each AFE8405 downconversion block can process two CDMA carriers or a single UMTS carrier. Signal

data is selected from one of four ports for real inputs, or two of four ports for complex inputs. Data from

the selected port(s) is multiplied with a complex, programmable, numerically controlled oscillator (NCO)

which tunes the signal of interest to baseband. The delay adjust and zero pad blocks permit adjustment of

the delay in the end-to-end channel. Zero padding interpolates the signal to the rxclk rate. Filtering

consists of a six-stage CIC filter which decimates the tuned data by a factor from 4 to 32, a compensating

FIR filter (CFIR) which decimates by a factor of two, followed by a programmable FIR filter (PFIR) which

does not decimate. The output interface block can be programmed to decimate by 2 if desired.

The RMS power meter measures the power within the channel bandwidth. The AGC automatically drives

the gain and keeps the magnitude of the signal at a user-specified level. This allows fewer bits to

represent the signal. The serial output interface formats and rounds the output data. Each of the

previously mentioned blocks is described in greater detail in the following sections.

Figure 7-15. Mixer Functional Block Diagram

The receive mixer translates the input (from one of the input signal sources) to baseband where

subsequent filtering is performed to isolate the signal of interest. The mixer is a complex multiplier that

accepts 18-bit I and 18-bit Q signal data from the receive input interface and 20-bit sine and cosine

sequences from the NCO. The NCO generates a mixing frequency (sometimes referred to as a local

oscillator, or LO) specified by the user so that the desired signal is tuned to 0 Hz.

A DDC channel can support one UMTS signal directly, or two CDMA channels at half the input rate. When

in CDMA mode, the path selection and the mixer tuning and phase of each channel can be set

independently. The mixer output produces two complex streams; one representing the signal path for the

A-side DDC, the other for the B-side. Each of these streams drives a channel delay and zero pad block.

The maximum input rate for UMTS is rxclk for either real or complex input data.

The maximum input rate in CDMA mode with real inputs is rxclk (remix_only is set, see the following).

The maximum input rate in CDMA mode with complex inputs is rxclk/2 due to sharing of multiplier

resources.

RECEIVE DIGITAL SIGNAL PROCESSING

Submit Documentation Feedback

AFE8405 Datasheet(PDF) 46 Page - Texas Instruments

AFE8405 Datasheet(HTML) 46 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL