AFE8405 datasheet(73/152 Pages) TI

73 / 152 page

AFE8405 GENERAL CONTROL

8.1 Microprocessor Interface Control Data, Address, and Strobes

AFE8405

14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER

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SLWS212 – OCTOBER 2008

The AFE8405 is configured over a bidirectional 16-bit parallel-data microprocessor control port. The

control port permits access to the control registers which configure the chip. The control registers are

organized using a paged-access scheme using 6 address lines. Half of the 64 addresses (address 32

through address 63) represent global registers. The other 32 (address 0 through address 31) are paged

registers. This arrangement permits accessing a large number of control registers using relatively few

address lines.

Global registers (Address 32 through Address 63) are used to read/write AFE8405 parameters that are

global in nature and can benefit from single read/write operations. Examples include chip status, reset,

sync options, checksum ramp parameters, interrupt sources, interrupt masks, 3-state controls and the

page register.

Global address 33 is the page register. Writing a 16-bit value to this register sets the page to which future

write or read operations performed. These paged registers contain the actual parameters that configure

the chip and are accessed by writing/reading address 0 through address 31.

The global 3-state register can be used to place the output drivers on the AFE8405 in the high-impedance

state, and also includes the capability of disabling the internal rxclk of the chip.

PROGRAMMING

VARIABLE

DESCRIPTION

rxclk_ena

Enables the internal rxclk when set. When cleared, the AFE8405 ignores the rxclk input signal and hold

the internal clock low.

3-state(10:0)

Various output pins are forced into the high-impedance state when these bits are asserted. See the

GBL_3STATE register description for pin groups to bit assignments.

arst_func

When asserted, the internal data path is held reset. The control register programming is not affected.

The microprocessor control bus consists of 16 bidirectional control data lines d[15:0], 6 address lines

a[5:0], a read enable line rd_n, a write enable line wr_n, and a chip enable line ce_n. These lines usually

interface to a microprocessor or DSP chip and are intended to look like a block of memory.

The interface can be operated in a three-pin control mode (using rd_n, wr_n and ce_n) or two-pin control

mode (using wr_n and ce_n with rd_n always low).

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AFE8405 GENERAL CONTROL

AFE8405 Datasheet(PDF) 73 Page - Texas Instruments