AFE8405 datasheet(11/152 Pages) TI

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4.2 Digital Receive Section Signals

AFE8405

14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER

www.ti.com

SLWS212 – OCTOBER 2008

Signal Name

Ball

Type

Description

rxclk

R22

Input

Receive digital section clock input

adcclk_a

n/a

Input

rxin_a_x input clock; connected to ADCA output clock

adcclk_b

n/a

Input

Not used, not connected internally

adcclk_c

AA11

Input

rxin_c_x input clock

adcclk_d

AB11

Input

rxin_d_x input clock

rxin_c_ovr

AB6

Input

ADC overflow/overrange bit for rxin_c

rxin_d_ovr

V12

Input

ADC overflow/overrange bit for rxin_d

dvga_a_5

Output

Digital VGA control output for ADC0 MSB

dvga_a_4

Output

Digital VGA control output for ADC0

dvga_a_3

Output

Digital VGA control output for ADC0

dvga_a_2

Output

Digital VGA control output for ADC0

dvga_a_1

Output

Digital VGA control output for ADC0

dvga_a_0

Output

Digital VGA control output for ADC0 LSB

dvga_b_5

Output

Not used

dvga_b_4

Output

Not used

dvga_b_3

Output

Not used

dvga_b_2

D10

Output

Not used

dvga_b_1

Output

Not used

dvga_b_0

Output

Not used

dvga_c_5

AA15

Output

Digital VGA control output for rxin_c MSB, test bus bit 1

dvga_c_4

AB15

Output

Digital VGA control output for rxin_c, test bus bit 0

dvga_c_3

V16

Output

Digital VGA control output for rxin_c, test bus bit 19

dvga_c_2

W16

Output

Digital VGA control output for rxin_c, test bus bit 18

dvga_c_1

Y16

Output

Digital VGA control output for rxin_c, test bus CLK

dvga_c_0

AA16

Output

Digital VGA control output for rxin_c LSB, test bus SYNC

dvga_d_5

AB16

Output

Digital VGA control output for rxin_d MSB, test bus AFLAG

dvga_d_4

V17

Output

Digital VGA control output for rxin_d

dvga_d_3

W17

Output

Digital VGA control output for rxin_d

dvga_d_2

AA17

Output

Digital VGA control output for rxin_d

dvga_d_1

AB17

Output

Digital VGA control output for rxin_d

dvga_d_0

V18

Output

Digital VGA control Output for rxin_d LSB

rxin_c_15

Input/output

Receive input data bus c bit 15 (MSB), test bus bit 17

rxin_c_14

AA7

Input/output

Receive input data bus c bit 14, test bus bit 16

rxin_c_13

AB7

Input/output

Receive input data bus c bit 13, test bus bit 15

rxin_c_12

Input/output

Receive input data bus c bit 12, test bus bit 14

rxin_c_11

V10

Input/output

Receive input data bus c bit 11, test bus bit 13

rxin_c_10

AA8

Input/output

Receive input data bus c bit 10, test bus bit 12

rxin_c_9

AB8

Input/output

Receive input data bus c bit 9, test bus bit 11

rxin_c_8

Input/output

Receive input data bus c bit 8, test bus bit 10

rxin_c_7

Input/output

Receive input data bus c bit 7, test bus bit 9

rxin_c_6

AA9

Input/output

Receive input data bus c bit 6, test bus bit 8

rxin_c_5

AB9

Input/output

Receive input data bus c bit 5, test bus bit 7

rxin_c_4

W10

Input/output

Receive input data bus c bit 4, test bus bit 6

rxin_c_3

Y10

Input/output

Receive input data bus c bit 3, test bus bit 5

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