AFE8405 datasheet(28/152 Pages) TI

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6.3 ADC Input Voltage Overstress

6.4 ADC Reference Circuit

S0179-01

20 W

refp

refm

iref

1 F

20 W

56.2kW

6.5 ADC Clock Input

AFE8405

14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER

SLWS212 – OCTOBER 2008

www.ti.com

The AFE8405 ADC can handle absolute maximum voltages of 3.6 V dc on the input pins inp and inm. For

dc inputs between 3.6 V and 3.8 V, a 25-

Ω resistor is required in series with the input pins. For inputs

above 3.8 V, the device can handle only transients, which must have less than 5% duty cycle of

overstress. The input pins connect internally to an ESD diode to AVDD, as well as a switched capacitor

circuit. The sampling capacitor of the switched capacitor circuit connects to the input pins through a switch

in the sample phase. In this phase, an input larger than 2.65 V would cause the switched capacitor circuit

to present an equivalent load of a forward biased diode to 2.65 V in series with a 60-

Ω impedance. Also,

beyond the voltage on AVDD, the ESD diode to AVDD starts to become forward biased.

In the phase where the sampling switch is off, the diode loading from the input switched capacitor circuit is

disconnected from the pin, while the ESD loading to AVDD is still present.

CAUTION

A violation of any of the previously stated conditions could damage the device (or

reduce its lifetime) either due to electromigration or gate oxide integrity. Care should

be taken not to expose the device to input overvoltage for extended periods of time,

as it may degrade device reliability.

The AFE8405 ADC has built-in internal reference generation, requiring no external circuitry on the printed

circuit board (PCB). For optimum performance, it is best to connect both refp and refm to ground with a

µF decoupling capacitor in series with a 20-Ω resistor, as shown in the Figure 6-6. In addition, an

external 56.2-k

Ω resistor should be connected from iref to AVSS to set the proper current for the operation

of the ADC, as shown in Figure 6-6. No capacitor should be connected between these pins; only the

56.2-k

Ω resistor should be used.

Figure 6-6. REFP, REFM, and IREF Connections for Optimum Performance

The AFE8405 ADC clock input can be driven with either a differential clock signal or a single-ended clock

input, with little or no difference in performance between the configurations. The common-mode voltage of

the clock inputs is set internally to cm using internal 5-k

Ω resistors that connect clkp and clkm to cm, as

shown in Figure 6-7.

ANALOG-TO-DIGITAL CONVERTERS

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