SH7101 datasheet(362/486 Pages) RENESAS

362 / 486 page

11. A/D Converter

Rev.2.00 Sep. 27, 2007 Page 328 of 448

REJ09B0394-0200

11.3

The A/D converter has the following registers. For details on register addresses and register states

in each operating mode, refer to section 18, List of Registers.

• A/D data register 8 (H/L) (ADDR8)

• A/D data register 9 (H/L) (ADDR9)

• A/D data register 10 (H/L) (ADDR10)

• A/D data register 11 (H/L) (ADDR11)

• A/D data register 12 (H/L) (ADDR12)

• A/D data register 13 (H/L) (ADDR13)

• A/D data register 14 (H/L) (ADDR14)

• A/D data register 15 (H/L) (ADDR15)

• A/D control/status register_0 (ADCSR_0)

• A/D control/status register_1 (ADCSR_1)

• A/D control register_0 (ADCR_0)

• A/D control register_1 (ADCR_1)

• A/D trigger select register (ADTSR)

11.3.1

A/D Data Registers 8 to 15 (ADDR8 to ADDR15)

ADDR are 16-bit read-only registers. The conversion result for each analog input channel is stored

in ADDR with the corresponding number. (For example, the conversion result of AN8 is stored in

ADDR8.)

The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0.

The data bus between the CPU and the A/D converter is 8 bits wide. The upper byte can be read

directly from the CPU, however the lower byte should be read via a temporary register. The

temporary register contents are transferred from the ADDR when the upper byte data is read.

When reading ADDR, read only the upper byte, or read in word unit. ADDR are initialized to

H'0000.

SH7101 Datasheet(PDF) 362 Page - Renesas Technology Corp