SH7101 datasheet(138/486 Pages) RENESAS

138 / 486 page

8. Multi-Function Timer Pulse Unit (MTU)

Rev.2.00 Sep. 27, 2007 Page 104 of 448

REJ09B0394-0200

8.3.3

Timer I/O Control Register (TIOR)

The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The MTU

has eight TIOR registers, two each for channels 0, 3, and 4, and one each for channels 1 and 2.

Care is required as TIOR is affected by the TMDR setting. The initial output specified by TIOR is

valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM

mode 2, the output at the point at which the counter is cleared to 0 is specified.

When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register

operates as a buffer register.

TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIORH_4

Bit

Bit Name

Initial value

R/W

Description

IOB3

IOB2

IOB1

IOB0

R/W

I/O Control B0 to B3

Specify the function of TGRB.

See the following tables.

TIORH_0: Table 8.10

TIOR_1:

Table 8.14

TIOR_2:

Table 8.16

TIORH_3: Table 8.18

TIORH_4: Table 8.22

IOA3

IOA2

IOA1

IOA0

R/W

I/O Control A0 to A3

Specify the function of TGRA.

See the following tables.

TIORH_0: Table 8.11

TIOR_1:

Table 8.15

TIOR_2:

Table 8.17

TIORH_3: Table 8.19

TIORH_4: Table 8.23

SH7101 Datasheet(PDF) 138 Page - Renesas Technology Corp

SH7101 Datasheet(HTML) 138 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL