SH7101 datasheet(156/486 Pages) RENESAS

156 / 486 page

8. Multi-Function Timer Pulse Unit (MTU)

Rev.2.00 Sep. 27, 2007 Page 122 of 448

REJ09B0394-0200

8.3.4

Timer Interrupt Enable Register (TIER)

The TIER registers are 8-bit readable/writable registers that control enabling or disabling of

interrupt requests for each channel. The MTU has five TIER registers, one for each channel.

Bit

Bit Name

Initial

value

R/W

Description

TTGE

R/W

A/D Conversion Start Request Enable

Enables or disables generation of A/D conversion start

requests by TGRA input capture/compare match.

0: A/D conversion start request generation disabled

1: A/D conversion start request generation enabled

⎯

Reserved

This bit is always read as 1, and should only be written

with 1.

TCIEU

R/W

Underflow Interrupt Enable

Enables or disables interrupt requests (TCIU) by the

TCFU flag when the TCFU flag in TSR is set to 1 in

channels 1 and 2.

In channels 0, 3, and 4, bit 5 is reserved. It is always

read as 0, and the write value should always be 0.

0: Interrupt requests (TCIU) by TCFU disabled

1: Interrupt requests (TCIU) by TCFU enabled

TCIEV

R/W

Overflow Interrupt Enable

Enables or disables interrupt requests (TCIV) by the

TCFV flag when the TCFV flag in TSR is set to 1.

0: Interrupt requests (TCIV) by TCFV disabled

1: Interrupt requests (TCIV) by TCFV enabled

TGIED

R/W

TGR Interrupt Enable D

Enables or disables interrupt requests (TGID) by the

TGFD bit when the TGFD bit in TSR is set to 1 in

channels 0, 3, and 4.

In channels 1 and 2, bit 3 is reserved. It is always read as

0, and the write value should always be 0.

0: Interrupt requests (TGID) by TGFD bit disabled

1: Interrupt requests (TGID) by TGFD bit enabled

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