SH7101 datasheet(158/486 Pages) RENESAS

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8. Multi-Function Timer Pulse Unit (MTU)

Rev.2.00 Sep. 27, 2007 Page 124 of 448

REJ09B0394-0200

8.3.5

Timer Status Register (TSR)

The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. The

MTU has five TSR registers, one for each channel.

Bit

Bit Name

Initial

value

R/W

Description

TCFD

Count Direction Flag

Status flag that shows the direction in which TCNT

counts in channels 1, 2, 3, and 4.

In channel 0, bit 7 is reserved. It is always read as 1, and

should only be written with 1.

0: TCNT counts down

1: TCNT counts up

⎯

Reserved

This bit is always read as 1, and should only be written

with 1.

TCFU

R/(W)

Underflow Flag

Status flag that indicates that TCNT underflow has

occurred when channels 1 and 2 are set to phase

counting mode. Only 0 can be written, for flag clearing.

In channels 0, 3, and 4, bit 5 is reserved. It is always

read as 0, and the write value should always be 0.

[Setting condition]

• When the TCNT value underflows (changes from

H'0000 to H'FFFF)

[Clearing condition]

• When 0 is written to TCFU after reading TCFU = 1

TCFV

R/(W)

Overflow Flag

Status flag that indicates that TCNT overflow has

occurred. Only 0 can be written, for flag clearing.

[Setting condition]

• When the TCNT value overflows (changes from

H'FFFF to H'0000)

In channel 4, when TCNT_4 is underflowed (changes

from H'0000 to H'0001) in complementary PWM

mode.

[Clearing condition]

• When 0 is written to TCFV after reading TCFV = 1

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