SH7101 datasheet(185/486 Pages) RENESAS

185 / 486 page

8. Multi-Function Timer Pulse Unit (MTU)

Rev.2.00 Sep. 27, 2007 Page 151 of 448

REJ09B0394-0200

• PWM mode 2

PWM output is generated using one TGR as the cycle register and the others as duty cycle

registers. The output specified in TIOR is performed by means of compare matches. Upon

counter clearing by a synchronization register compare match, the output value of each pin is

the initial value set in TIOR. If the set values of the cycle and duty cycle registers are identical,

the output value does not change when a compare match occurs.

In PWM mode 2, a maximum 8-phase PWM output is possible in combination use with

synchronous operation.

The correspondence between PWM output pins and registers is shown in table 8.31.

Table 8.31

PWM Output Registers and Output Pins

Output Pins

Channel

Registers

PWM Mode 1

PWM Mode 2

TGRA_0

TIOC0A

TGRB_0

TIOC0A

TIOC0B

TGRC_0

TIOC0C

TGRD_0

TIOC0C

TIOC0D

TGRA_1

TIOC1A

TGRB_1

TIOC1A

TIOC1B

TGRA_2

TIOC2A

TGRB_2

TIOC2A

TIOC2B

TGRA_3

Cannot be set

TGRB_3

TIOC3A

Cannot be set

TGRC_3

Cannot be set

TGRD_3

TIOC3C

Cannot be set

TGRA_4

Cannot be set

TGRB_4

TIOC4A

Cannot be set

TGRC_4

TIOC4C

Cannot be set

TGRD_4

Cannot be set

Note:

In PWM mode 2, PWM output is not possible for the TGR register in which the period is set.

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