SH7101 datasheet(211/486 Pages) RENESAS

211 / 486 page

8. Multi-Function Timer Pulse Unit (MTU)

Rev.2.00 Sep. 27, 2007 Page 177 of 448

REJ09B0394-0200

Dead Time Setting: In complementary PWM mode, PWM pulses are output with a non-

overlapping relationship between the positive and negative phases. This non-overlap time is called

the dead time.

The non-overlap time is set in the timer dead time data register (TDDR). The value set in TDDR is

used as the TCNT_3 counter start value, and creates non-overlap between TCNT_3 and TCNT_4.

Complementary PWM mode should be cleared before changing the contents of TDDR.

PWM Cycle Setting: In complementary PWM mode, the PWM pulse cycle is set in two

registers

⎯TGRA_3, in which the TCNT_3 upper limit value is set, and TCDR, in which the

TCNT_4 upper limit value is set. The settings should be made so as to achieve the following

relationship between these two registers:

TGRA_3 set value = TCDR set value + TDDR set value

The TGRA_3 and TCDR settings are made by setting the values in buffer registers TGRC_3 and

TCBR. The values set in TGRC_3 and TCBR are transferred simultaneously to TGRA_3 and

TCDR in accordance with the transfer timing selected with bits MD3 to MD0 in the timer mode

The updated PWM cycle is reflected from the next cycle when the data update is performed at the

crest, and from the current cycle when performed in the trough. Figure 8.36 illustrates the

operation when the PWM cycle is updated at the crest.

See the following section, Register data updating, for the method of updating the data in each

buffer register.

SH7101 Datasheet(PDF) 211 Page - Renesas Technology Corp