3886 datasheet(111/380 Pages) RENESAS

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HARDWARE

1-86

3886 Group User’s Manual

q CPU reprogramming mode operation procedure

The operation procedure in CPU reprogramming mode is de-

scribed below.

< Beginning procedure >

➀ Apply 0 V to the CNVss/VPP pin for reset release.

➁ After CPU reprogramming mode control program is transferred to

internal RAM, jump to this control program on RAM. (The follow-

ing operations are controlled by this control program).

➂ Set “1" to the CPU reprogramming mode select bit.

➃ Apply VPPH to the CNVSS/VPP pin.

➄ Wait till CNVSS/VPP pin becomes 12 V.

➅ Read the CPU reprogramming mode monitor flag to confirm

whether the CPU reprogramming mode is valid.

➆ The operation of the flash memory is executed by software-com-

mand-writing to the flash command register .

Note: The following are necessary other than this:

•Control for data which is input from the external (serial I/O

etc.) and to be programmed to the flash memory

•Initial setting for ports etc.

•Writing to the watchdog timer

< Release procedure >

➀ Apply 0V to the CNVSS/VPP pin.

➁ Wait till CNVSS/VPP pin becomes 0V.

➂ Set the CPU reprogramming mode select bit to “0.”

Each software command is explained as follows.

q Read command

When “0016" is written to the flash command register,

the

M38869FFAHP/GP enters the read mode. The contents of the

corresponding address can be read by reading the flash memory

(For instance, with the LDA instruction etc.) under this condition.

The read mode is maintained until another command code is written

to the flash command register. Accordingly, after setting the read

mode once, the contents of the flash memory can continuously be

read.

After reset and after the reset command is executed, the read

mode is set.

Fig. 82 Flash command register bit configuration

Fig. 83 CPU mode register bit configuration in CPU rewriting

mode

FUNCTIONAL DESCRIPTION

Writing of software command

“0016”

“4016”

“C016”

“2016” + “2016”

“A016”

“FF16” + “FF16”

• Read command

• Program command

• Program verify command

• Erase command

• Erase verify command

• Reset command

Note: The flash command register is write-only register.

Flash command register

(FCMD : address 0FFF16)

Processor mode bits

b1 b0

0 : Single-chip mode

1 : Not available

X : Not available

Port XC switch bit

0 : I/O port function (stop oscillating)

1 : XCIN–XCOUT oscillating function

Main clock (XIN–XOUT) stop bit

0 : Oscillating

1 : Stopped

Main clock division ratio selection bits

b7 b6

0 :

φ = f(XIN)/2 (high-speed mode)

1 :

φ = f(XIN)/8 (middle-speed mode)

0 :

φ = f(XCIN)/2 (low-speed mode)

1 : Not available

CPU mode register

(CPUM : address 003B16)

Stack page selection bit

0 : 0 page

1 : 1 page

Fix this bit to “1”.

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