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3886 Datasheet(PDF) 134 Page - Renesas Technology Corp |
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3886 Datasheet(HTML) 134 Page - Renesas Technology Corp |
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134 / 380 page  3886 Group User’s Manual APPLICATION 2-17 2.2 Interrupt (3) Interrupt disable flag The interrupt disable flag is allocated to bit 2 of the processor status register. The interrupt disable flag controls the acceptance of interrupt request except BRK instruction. When this flag is “1”, the acceptance of interrupt requests is disabled. When the flag is “0”, the acceptance of interrupt requests is enabled. This flag is set to “1” with the SEI instruction and is set to “0” with the CLI instruction. When a main routine branches to an interrupt processing routine, this flag is automatically set to “1”, so that multiple interrupts are disabled. To use multiple interrupts, set this flag to “0” with the CLI instruction within the interrupt processing routine. Figure 2.2.14 shows an example of multiple interrupts. Table 2.2.2 List of interrupt bits according to interrupt source INT0/Input buffer full INT1/Output buffer empty Serial I/O1 reception Serial I/O1 transmission/SCL, SDA Timer X Timer Y Timer 1 Timer 2 CNTR0/SCL, SDA CNTR1/Key-on wake-up Serial I/O2/I2C INT2/I2C INT3 INT4 A-D converter/Key-on wake-up Interrupt enable bit Address 003E16 003E16 003E16 003E16 003E16 003E16 003E16 003E16 003F16 003F16 003F16 003F16 003F16 003F16 003F16 Bit b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 Interrupt request bit Address 003C16 003C16 003C16 003C16 003C16 003C16 003C16 003C16 003D16 003D16 003D16 003D16 003D16 003D16 003D16 Bit b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 Interrupt source |
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