3886 datasheet(196/380 Pages) RENESAS

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3886 Group User’s Manual

APPLICATION

2-79

2.5 Multi-master I2C-BUS interface

Table 2.5.1 Set value of I2C clock control register and SCL frequency

SCL frequency (Note 1)

(at

φ = 4 MHz, unit : kHz)

Setting value of

CCR4–CCR0

Standard clock

mode

Setting disabled

High-speed

clock mode

CCR4

CCR3

CCR2

CCR1

CCR0

Setting disabled

34.5

33.3

32.3

100

83.3

333

250

400 (Note 3)

166

– (Note 2)

500/CCR value

1000/CCR value

17.2

16.6

16.1

Notes 1: Duty of SCL clock output is 50 %. The duty becomes 35 to 45 % only when the high-speed clock mode is selected

and CCR value = 5 (400 kHz, at

φ = 4 MHz). “H” duration of the clock fluctuates from –4 to +2 machine cycles in

the standard clock mode, and fluctuates from –2 to +2 machine cycles in the high-speed clock mode. In the case of

negative fluctuation, the frequency does not increase because “L” duration is extended instead of “H” duration

reduction.

These are value when SCL clock synchronization by the synchronous function is not performed. CCR value is the

decimal notation value of the SCL frequency control bits CCR4 to CCR0.

2: Each value of SCL frequency exceeds the limit at

φ = 4 MHz or more. When using these setting value, use φ of

4 MHz or less.

3: The data formula of SCL frequency is described below:

φ/(8 ✕ CCR value) Standard clock mode

φ/(4 ✕ CCR value) High-speed clock mode (CCR value ≠ 5)

φ/(2 ✕ CCR value) High-speed clock mode (CCR value = 5)

Do not set 0 to 2 as CCR value regardless of

φ frequency.

Set 100 kHz (max.) in the standard clock mode and 400 kHz (max.) in the high-speed clock mode to the SCL

frequency by setting the SCL frequency control bits CCR4 to CCR0.

Fig. 2.5.6 Structure of I2C clock control register

b7b6b5b4b3b2b1b0

Function

At reset

Name

I2C clock control register (S2) [Address : 1616]

I2C clock control register

SCL frequency control bits

(CCR0, CCR1, CCR2, CCR3,

CCR4)

0 : Standard clock mode

1 : High-speed clock mode

SCL mode specification bit

(FAST MODE)

ACK bit (ACK BIT)

ACK clock bit (ACK)

0 : ACK is returned

1 : ACK is not returned

0 : No ACK clock

1 : ACK clock

Refer to Table 2.5.1

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