3886 datasheet(195/380 Pages) RENESAS

195 / 380 page

2-78

3886 Group User’s Manual

APPLICATION

2.5 Multi-master I2C-BUS interface

Fig. 2.5.5 Structure of I2C control register

I2C control register

b7b6b5b4b3b2b1b0

Function

At reset

Name

I2C control register (S1D) [Address :1516]

Bit counter (Number of

transmit/receive bits)

(BC0, BC1, BC2)

0 0 0 : 8

0 0 1 : 7

0 1 0 : 6

0 1 1 : 5

1 0 0 : 4

1 0 1 : 3

1 1 0 : 2

1 1 1 : 1

b2 b1 b0

I2C-BUS interface enable bit

(ES0)

0 : Disabled

1 : Enabled

Data format selection bit

(ALS)

0 : Addressing format

1 : Free data format

Addressing format selection

bit (10 BIT SAD)

0 : 7-bit addressing format

1 : 10-bit addressing format

System clock stop selection

bit (CLKSTP)

I2C-BUS interface pin input

level selection bit (TISS)

0 : System clock stop when

executing WIT or STP

instruction

1 : Not system clock stop when

executing WIT instruction

(Do not use the STP

instruction.)

0 : CMOS input

1 : SMBUS input

Notes : When the read-modify-write instruction is executed for this register at detecting

the START condition or at completing the byte transfer, data may become a

value not intended.

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