3886 datasheet(257/380 Pages) RENESAS

257 / 380 page

2-140

3886 Group User’s Manual

APPLICATION

2.10 Watchdog timer

Fig. 2.10.6 Control procedure

Fig. 2.10.5 Relevant registers setting

2.10.4 Notes on watchdog timer

qMake sure that the watchdog timer does not underflow while waiting Stop release, because the watchdog

timer keeps counting during that term.

qWhen the STP instruction disable bit has been set to “1”, it is impossible to switch it to “0” by a program.

CPUM0

WDTCON

CPU mode register (address 3B16)

Processor mode: Single-chip mode

Main clock (XIN-XOUT): Operating

Main clock division ratio: f(XIN)/2 (high-speed mode)

Watchdog timer H (for read-out of high-order 6 bits)

Watchdog timer control register (address 1E16)

Enable STP instruction

Watchdog timer H count source: Watchdog timer L underflow

Initialization

SEI

CLT

CLD

CPUM (address 3B16)

CLI

000XXX002

WDTCON (address 1E16), bit7,bit6

002

RESET

Main processing

•All interrupts disabled

•Processor mode: Single-chip mode

•Main clock f(XIN): Operating

•High-speed mode selected as main clock division ratio

•Interrupts enabled

•Watchdog timer L underflow selected as Watchdog

timer H count source

•STP instruction enabled

3886 Datasheet(PDF) 257 Page - Renesas Technology Corp