32182 datasheet(108/755 Pages) RENESAS

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4-13

EIT

32182 Group User’s Manual (Rev.1.0)

4.8 Exception Processing

Figure 4.8.2 Example of a Return Address for Address Exception (AE)

(4) Branching to the EIT vector entry

The CPU branches to the address H’0000 0030 in the user space. This is the last operation performed in

hardware preprocessing.

(5) Jumping from the EIT vector entry to the user-created handler

The CPU executes the BRA instruction written by the user at the address H’0000 0030 of the EIT vector

entry to jump to the start address of the user-created handler. At the beginning of the user-created EIT

handler, first save the BPC and PSW registers and the necessary general-purpose registers to the stack.

Also, save the accumulator and FPSR register as necessary.

(6) Returning from the EIT handler

At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction.

When the RTE instruction is executed, hardware postprocessing is automatically performed. At this time,

the CPU restarts from a word-boundary instruction including the instruction that generated an AE (see Figure

4.8.2). Except when using address exceptions intentionally, occurrence of an address exception suggests

that the system has some fatal fault already existing in it. In such a case, therefore, do not return from the

address exception handler to the program that was being executed when the exception occurred.

4.8.3 Floating-Point Exception (FPE)

[OccurrenceConditions]

Floating-Point Exception (FPE) occurs when Unimplemented Exception (UIPL) or one of the five exceptions

specified in IEEE 754 standards (OVF, UDF, IXCT, DIV0 or IVLD) is detected.

Note, however, that the EIT processing described below is executed only when the exception that occurred

is one whose exception enable bit in the FPSR register is set to "1" or an unimplemented exception.

[EIT Processing]

(1) Saving SM, IE and C bits

The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC.

BSM

←

BIE

←

(2) Updating SM, IE and C bits

The PSW register’s SM, IE and C bits are updated as shown below.

←

Unchanged

←

H'00

Address

AE occurred

H'04

H'08

H'0C

H'00

Address

AE occurred

H'04

H'08

H'0C

BPC

H'06

BPC

H'04

Return

address

Return

address

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