| Electronic Components Datasheet Search |
|
7480 Datasheet(PDF) 169 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
7480 Datasheet(HTML) 169 Page - Renesas Technology Corp |
|
169 / 337 page ![]() 7480 Group and 7481 Group User's Manual 1-152 HARDWARE Figure 1.16.5 Internal Processing Sequence during Reset by Watchdog Timer Countermeasures with Watchdog Timer against Runaway Watchdog timer H is written to with the main routine, etc., to keep bit 7 from going to ‘0.’ (keep it at ‘1’). In case of a program runaway by noise, watchdog timer H is not written to, so that bit 7 becomes ‘0’ and the CPU returns to the reset state. Operations in Stop and Wait Modes • When the STP instruction is executed to enter the stop mode, the f(XIN) stops, causing the watchdog timer to stop counting. When the stop mode is terminated, the watchdog timer starts counting in response to the restarting of f(XIN) oscillation. • When the WIT instruction is executed to enter the wait mode, CPU stops operating, whereas the watchdog timer continues counting because the oscillation of f(XIN) does not stop. Note: The watchdog timer continues counting even during the oscillator start-up stabilization time (2048 cycles of the XIN pin input signal) after the stop mode is terminated, and the wait mode. Write to watchdog timer in order to prevent bit 7 of watchdog timer H from going to ‘0’. In the 7480 Group and 7481 Group, the valid/invalid of the STP and WIT instructions can be selected. Invalidating these instructions causes a runaway to be detected more effectively when the watchdog timer is used. For details on the setting of the valid/invalid of the stop and wait modes and the STP and WIT instructions, refer to Section 1.19 Power Saving Function. 1.16 Watchdog Timer XIN pin Internal clock φ Internal reset signal Address bus Data bus SYNC pin FFFE16 FFFF16 AL,AH AL AH Bit 7 of Watchdog Timer H changes from ‘1’ to ‘0’. 2048 cycles of XIN pin input signal Internal Clock φ : AH, AL : SYNC : : Basic clock frequency of CPU, f(XIN)/2 (high-speed mode) after system is released from reset. Jump addresses stored in reset vector area. CPU opcode fetch cycle (it cannot be examined externally because it is an internal signal). Undefined |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |