7480 datasheet(167/337 Pages) RENESAS

167 / 337 page

7480 Group and 7481 Group User's Manual

1-150

HARDWARE

1.16 Watchdog Timer

Figure 1.16.3 Watchdog Timer H

(1)

Watchdog Timer H

Watchdog timer H indicates the high-order 8 bits of the count value of the watchdog timer.

Figure 1.16.3 shows the watchdog timer H.

(2)

CPU Mode Register

This register consists of the bits that select a stack page and an internal clock, as well as the bit that

selects a count source of the watchdog timer.

Figure 1.16.4 shows the CPU mode register.

Figure 1.16.4 CPU Mode Register

CPU mode register

b4 b3 b2 b1 b0

Name

Function

At reset

Undefined

CPU mode register (CPUM) [Address 00FB16]

Fix these bits to ‘0’

Stack page selection bit

(Note)

0 : Zero page

1 : 1 page

Watchdog timer L count

source selection bit

0 : f(XIN)/8

1 : f(XIN)/16

Clock division

ratio selection bit

0 : f(XIN)/2 (high-speed mode)

1 : f(XIN)/8 (medium-speed mode)

Not implemented. Writing to this bit is disabled.

This bit is undefined at reading.

Not implemented. Writing to this bit is disabled.

This bit is undefined at reading.

Note: In the products whose RAM size is 192 bytes or less, set this bit to ‘0’.

Not implemented. Writing to this bit is disabled.

This bit is undefined at reading.

Undefined

Watchdog timer H

b4 b3 b2 b1 b0

Function

At reset

Watchdog timer H (WDTH) [Address 00EF16]

The high-order count value of watchdog timer is indicated.

The following value is set by writing arbitrary data.

• watchdog timer L

← ‘7F16’

• watchdog timer H

← ‘FF16’

Note:

Note

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