7480 datasheet(170/337 Pages) RENESAS

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7480 Group and 7481 Group User's Manual

1-153

HARDWARE

1.16 Watchdog Timer

1.16.4 Setting of Watchdog Timer

Figure 1.16.6 shows the setting of the watchdog timer.

Figure 1.16.6 Setting of Watchdog Timer

1.16.5 Notes on Usage

Pay attention to the following notes when the watchdog timer is used.

Write to watchdog timer in the main routine in order to prevent bit 7 of watchdog timer H from going to

‘0’.

The watchdog timer continues counting even during the oscillator start-up stabilization time (2048 cycles

of the XIN pin input signal) after the stop mode is terminated, and the wait mode. Write to watchdog timer

in order to prevent bit 7 of watchdog timer H from going to ‘0’.

Do not operate the watchdog timer during system evaluation.

Procedure 1 Selecting watchdog timer L count source

CPU mode register (CPUM) [Address 00FB16]

Arbitrary data (Note 2)

Procedure 2 Writing to watchdog timer H (Note 1)

Watchdog timer H (WDTH) [Address 00EF16]

FF16

Notes 1: Writing to watchdog timer H starts counting.

2: The following values are set regardless of written data.

• Watchdog Timer L

← ‘7F16’

• Watchdog Timer H

← ‘FF16’

Note: Internal reset occurs if bit 7 of watchdog timer H becomes ‘0’. Therefore, write to watchdog timer H

in the main routine in order to prevent bit 7 of watchdog timer H from going to ‘0’.

Since the timer counts for the start-up stabilization time (2048 cycles of the XIN pin input signal),

bit 7 of watchdog timer H must not be ‘0’ during this period.

Watchdog timer L count soure selection

0: f(XIN)/8

1: f(XIN)/16

7480 Datasheet(PDF) 170 Page - Renesas Technology Corp