7480 datasheet(203/337 Pages) RENESAS

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7480 Group and 7481 Group User's Manual

1-186

HARDWARE

1.21 Electrical Characteristics

Table 1.21.9 Recommended Operating Conditions of 7481 Group (2) (Note 1)

Unit

MHz

kHz

MHz

Limits

Symbol

IOH(sum)

IOL(sum)

IOH(peak)

IOL(peak)

IOH(avg)

IOL(avg)

f(CNTR)

f(SCLK)

f(XIN)

Min.

Max.

–30

–10

–5

500

250

2.2VCC–2.0

Typ.

when selecting clock

synchronous serial I/O

when selecting

UART

VCC = 4.5V to 5.5V

VCC = 2.7V to 4.5V

f(XIN) = 8 MHz

f(XIN) = 4 MHz

f(XIN) = 8 MHz

f(XIN) = 4 MHz

f(XIN) = 8 MHz

f(XIN) = 4 MHz

Notes 1: VCC = 2.7 V to 5.5 V, VSS = 0 V, and Ta = –20

°C to 85 °C (Ta = –40 ° C to 85 °C for extended

operating temperature range version), unless otherwise noted.

For the clamping diodes of port P4, refer to (4) Level Shift Ports in Section 1.10.3 I/O Ports.

2: Output average currents IOH(avg) and IOL(avg) are average values for a period of 100 ms.

3: The frequency is the value at a 50% duty cycle.

4: Connect a bypass capacitor of capacity 0.1

µF between VCC and VSS, and one of capacity 0.01µF

between VREF and VSS.

Parameter

HIGH output sum current P00–P07

HIGH output sum current P10–P17

LOW output sum current P00–P07, P40–P43, P50–P52

LOW output sum current P10–P17, P53

HIGH output peak current P00–P07, P10–P17

LOW output peak current P00–P07, P10–P17, P40–P43, P50–P53

HIGH output average current P00–P07, P10–P17 (Note 2)

LOW output average current

P00–P07, P10–P17, P40–P43, P50–P53 (Note 2)

Timer input frequency CNTR0 (P40)

CNTR1 (P41) (Note 3)

Serial I/O

clock input frequency

SCLK (P16)

(Note 3)

Clock input oscillation

frequency (Note 3)

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