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GL848 Datasheet(PDF) 7 Page - GENESYS LOGIC

Part # GL848
Description  High Speed USB 2.0
PDF  85 Pages
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Manufacturer  GENESYS [GENESYS LOGIC]
Direct Link  http://www.genesyslogic.com
Logo GENESYS - GENESYS LOGIC

GL848 Datasheet(HTML) 7 Page - GENESYS LOGIC

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GL848 High Speed USB2.0 2-in-1 Scanner Controller With Fast ADF
©2000-2007 Genesys Logic Inc. - All rights reserved.
Page 7
CHAPTER 2
FEATURES
Highly integrated scanner controller chip (2-in-1; Scanner Controller and USB 2.0 Interface)
USB 2.0 High Speed (480Mbit) compliant
Designed for sheetfed, flatbed and transparency scanners
Designed for self-power and bus-power application
Embedded RISC CPU for USB protocol handling
Support single AFE for dual head scanning
12MHz low frequency clock input for better EMI
Adjustable working clock of scanner controller for different usage (12M, 24M, 30M, 40M, 48M, 60MHz)
Supports linear or stagger CCD, such as NEC, Toshiba or Sony CCD
Available sensor types: 600, 1200, 2400, 3200, 3600, 4800 and 9600 dpi color CIS or CCD
Multi-TG control for CCD (separately controls the R/G/B exposure time)
Shutter-control for CCD (separately controls the R/G/B exposure time)
Supports two scanning types: pixel-by-pixel (pixel rate), line-by-line (line rate)
Support 48-bits color, 16-bits gray and 1-bit line-art
“True gray” with R, G and B weightings
16 bits white/dark shading and 16 bits Gamma correction
Supports RS232 interface for special applications
Supports EEPROM (93C46) interface for special applications
Supports ADF (Auto-Document-Feeder) function with document, ADF and cover sensors
Supports auto-ADF with automatically feeding in, automatically scanning and automatically feeding out
Lines packing for stagger CCD or R/G/B line differences
Fine CDS sampling adjustment to avoid the digital noise influence (8.33ns adjustment)
Digital average and hardware deletion for various resolutions
Hardware deletion for various resolutions (from 9600~1dpi with 1dpi decrement)
Supports 1M*16, 4M*16, 8M*16, 16M*16 and 32M*16 SDRAM
Supports up to 1 G bits size SDRAM (implements two SDRAM)
Supports 5 acceleration/deceleration motor tables for high speed motor moving and wall hitting protection
Supports controllable bipolar motor in full, half, quarter and eighth steps moving
Supports controllable unipolar motor in full and half steps moving
Supports V-reference automatic control for motor driver Ics
Build-in PWM control phase for unipolar motors
Programmable dummy lines to resolve start/stop (discontinuous) problem
Watchdog protection for lamp, motor and ASIC
Lamp time-out (sleeping) control
Supports 21 GPIO pins and 5 GPO pins for I/O control



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