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GL848 Datasheet(PDF) 32 Page - GENESYS LOGIC |
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GL848 Datasheet(HTML) 32 Page - GENESYS LOGIC |
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32 / 85 page  GL848 High Speed USB2.0 2-in-1 Scanner Controller With Fast ADF ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 32 BUFSEL7 BUFSEL6 BUFSEL5 BUFSEL4 BUFSEL3 BUFSEL2 BUFSEL1 BUFSEL0 R/W R/W R/W R/W R/W R/W R/W R/W 7-0 BUFSEL [7:0] To set buffer condition. When buffer is full, scanner will stop and wait for host to read out image data from SDRAM. The valid data count (has not been read) is represented by VALIDWORD (in word). If VALIDWORD < buffer condition, then the scanner will re-start to scan. Following are the units of this register under various SDRAM size. 16M bits SDRAM : 4k words 64M bits SDRAM : 16k words 128M bits SDRAM : 32K words 256M bits SDRAM : 64K words 512M bits SDRAM : 128K words Offset 21h ……..……………………………………..…………..….…..…….…. Default value = 8’h00 STEPNO7 STEPNO6 STEPNO5 STEPNO4 STEPNO3 STEPNO2 STEPNO1 STEPNO0 R/W R/W R/W R/W R/W R/W R/W R/W 7-0 STEPNO [7:0] Steps number of “table one” for the acceleration/deceleration of scanning moving. Please refer to section 6.19 and the descriptions of Reg24 & Reg6A. Note: 1.It cannot be programmed to logic zero. 2.it can be multiplied by2* STEPTIM Offset 22h ……..……………………………………..…………..….…..…….…. Default value = 8’h00 FWDSTEP7 FWDSTEP6 FWDSTEP5 FWDSTEP4 FWDSTEP3 FWDSTEP2 FWDSTEP1 FWDSTEP0 R/W R/W R/W R/W R/W R/W R/W R/W 7-0 FWDSTEP [7:0] Steps number for forward moving when buffer condition is met. Please refer to section 6.19 and the descriptions of Reg20 & Reg24. Note: 1.It cannot be programmed to logic zero. 2.it can be multiplied by2* STEPTIM Offset 23h ……..……………………………………..…………..….…..…….…. Default value = 8’h00 BWDSTEP7 BWDSTEP6 BWDSTEP5 BWDSTEP4 BWDSTEP3 BWDSTEP2 BWDSTEP1 BWDSTEP0 R/W R/W R/W R/W R/W R/W R/W R/W 7-0 BWDSTEP [7:0] Steps number for backward moving when image buffer is full. Please refer to section 6.19 and the descriptions of Reg24. Note: 1.It cannot be programmed to logic zero. 2.it can be multiplied by2* STEPTIM Offset 24h ……..……………………………………..…………..….…..…….…. Default value = 8’h00 FASTNO7 FASTNO6 FASTNO5 FASTNO4 FASTNO3 FASTNO2 FASTNO1 FASTNO0 R/W R/W R/W R/W R/W R/W R/W R/W 7-0 FASTNO [7:0] Steps number of “table two” for the acceleration/deceleration when image buffer is full. Please refer to section 6.19 and the descriptions of Reg20. Note: It cannot be programmed to logic zero. |
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