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GL848 Datasheet(PDF) 24 Page - GENESYS LOGIC |
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GL848 Datasheet(HTML) 24 Page - GENESYS LOGIC |
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24 / 85 page ![]() GL848 High Speed USB2.0 2-in-1 Scanner Controller With Fast ADF ©2000-2007 Genesys Logic Inc. - All rights reserved. Page 24 Color scanning : 24 bits image with gamma correction 48 bits image without gamma correction Gray scanning : 8 bits image with gamma correction 16 bits image without gamma correction Line art scanning : 1 bit image with gamma correction 4 PWRBIT The hardware will reset this bit during power-on initial process. It can be set and checked by S/W to know if the power had been turned off or not. Default is reset. 3 GAIN4 0 Digital shading gain=8 times system. 1 Digital shading gain=4 times system. Note: If you want to get more precise image quality,you can set GAIN4 bit. 2-0 OPTEST [2:0] Select ASIC operation type. 000 Set normal mode to capture AFE image. 001 Set SDRAM bank testing and power-on moving testing for ASIC simulation 010 Pixel count pattern for ASIC image test. 011 Line count pattern for ASIC image test. 100 Counter and adder test for ASIC simulation test. 101 Reserved. 110 Reserved. 111 Reserved. Offset 07h ……………………………………………..…………..……..………. Default value = 8’h00 LAMPSIM RESERVE6 RESERVE5 RESERVE4 RESERVE3 RESERVE2 RESERVE1 RESERVE0 R/W R/W R/W R/W R/W R/W R/W R/W 7 LAMPSIM for timer simulation 6-0 RESERVE [6:0] These bits are reserved for special application Note: Please do not write other values than 00H into this register under normal condition. Offset 08h ……………………………………………..…………..……..………. Default value = 8’h00 DRAM2X SCNUMENB MPENB CIS_LINE X X X ENB24M R/W R/W R/W R/W X X X R/W 7 DRAM2X 0 Select single chip of SDRAM 1 Enable two chips of SDRAM 6 SCNUMENB Enable page count which is stored in memory for ADF operation 5 MPENB Enable motor phase generating function which is stored in memory 4 CIS_LINE Set CIS_LINE to “1” and set CISSET to “1” at the same time to enable CIS scanning, and work on line by line mode. 0 ENB24M 0 Disable 24MHz CCD/CIS Clock output 1 Enable 24MHz CCD/CIS Clock output Offset 09h ……………………………………………..…………..……..………. Default value = 8’h00 MCNTSET1 MCNTSET0 EVEN1ST BLINE1ST BACKSCAN X SHORTTG X R/W R/W R/W R/W R/W X R/W X 7-6 MCNTSET [1:0] To select the unit of motor table counter. 00 Pixel count. 01 System clock*2. 10 System clock*3. |
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