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TUSB7320 Datasheet(PDF) 23 Page - Texas Instruments |
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TUSB7320 Datasheet(HTML) 23 Page - Texas Instruments |
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23 / 115 page  SCL SDA VDD33 A0 A1 A2 SCL SDA TUSB73x0 Serial EEPROM TUSB7320, TUSB7340 www.ti.com SLLSE76J – MARCH 2011 – REVISED MAY 2012 The host controller implements a two-terminal serial interface with one clock signal (SCL) and one data signal (SDA). The SCL signal is a unidirectional output from the host controller and the SDA signal is bidirectional. Both are open-drain signals and require pull-up resistors. The host controller is a bus master device and drives SCL at approximately 60 kHz during data transfers and places SCL in a high- impedance state (0 frequency) during bus idle states. The serial EEPROM is a bus slave device and must acknowledge a slave address equal to A0h. Figure 3-3 illustrates an example application implementing the two-wire serial bus. Figure 3-3. Serial EEPROM Application Copyright © 2011–2012, Texas Instruments Incorporated FEATURE/PROTOCOL DESCRIPTIONS 23 Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 |
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