TUSB7320 datasheet(51/115 Pages) TI1

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TUSB7320, TUSB7340

www.ti.com

SLLSE76J – MARCH 2011 – REVISED MAY 2012

Table 4-70. Link Control 2 Register Description

Bit

Field Name

Access

Description

15:13

RSVD

Reserved. Returns zeros when read.

Compliance De-Emphasis. This bit is sticky and is only reset by a Global

COMPLIANCE_DEEMPH*

Reset.

COMPLIANCE_SOS*

Compliance SOS. This bit is sticky and is only reset by a Global Reset.

Enter Modified Compliance. This bit is sticky and is only reset by a

ENT_MOD_COMPLIANCE*

Global Reset.

9:7

TRANSMIT_MARGIN*

Transmit Margin. This bit is sticky and is only reset by a Global Reset.

SEL_DEEMPH

Selectable De-Emphasis. This bit has no function and is read only zero.

Hardware Autonomous Speed Disable. This bit is read only zero since

HW_AUTO_SPEED_DIS

this function is not supported.

ENTER_COMPL*

Enter Compliance. This bit is sticky and is only reset by a Global Reset.

3:0

TGT_LINK_SPEED*

Target Link Speed. This bit is sticky and is only reset by a Global Reset.

4.48 Link Status 2 Register

The Link Status 2 Register indicates current state of the PCI Express Link.

PCI register offset: A2h

Default value: 000xh

Table 4-71. PCI Register A2h

Bit

No.

Reset

State

Table 4-72. Link Status 2 Register Description

Bit

Field Name

Access

Description

15:1

RSVD

Reserved. Returns zeros when read.

DEEMPH_LEVEL

Current De-Emphasis Level.

4.49 Serial Bus Data Register

The Serial Bus Data register is used to read and write data on the serial bus interface. When writing data

to the serial bus, this register must be written before writing to the Serial Bus Address register to initiate

the cycle. When reading data from the serial bus, this register will contain the data read after the

REQBUSY (bit 5 Serial Bus Control Register) bit is cleared. This register is reset by a PCI Express reset

(PERST#), a GRST#, or the internally-generated power-on reset.

PCI register offset: B0h

Default value: 00h

Table 4-73. PCI Register B0h

Bit No.

Reset State

CLASSIC PCI CONFIGURATION SPACE

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