TUSB7320 datasheet(48/115 Pages) TI1

48 / 115 page

TUSB7320, TUSB7340

SLLSE76J – MARCH 2011 – REVISED MAY 2012

www.ti.com

Table 4-60. Link Capabilities Register Description (continued)

Clock Power Management. This bit is hardwired to 1 to indicate that the

CLK_PM

TUSB73X0 supports Clock Power Management through the CLKREQ#

protocol.

L1 Exit Latency. This field indicates the time that it takes to transition

from the L1 state to the L0 state. The value reported by this field is

17:15

L1_LATENCY

determined by either the L1_EXIT_LAT_ASYNC field or the

L1_EXIT_LAT_COMMON field in the General Control Register 0.

L0s Exit Latency. This field indicates the time that it takes to transition

from the L0s state to the L0 state. The value reported by this field is

14:12

L0S_LATENCY

determined by either the L0s_EXIT_LAT_ASYNC field or the

L0s_EXIT_LAT_COMMON field in the General Control Register 0.

Active State Link PM Support. This field indicates the level of active state

power management that the TUSB73X0 supports. The value 11b

11:10

ASLPMS

indicates support for both L0s and L1 through active state power

management.

Maximum Link Width. This field is encoded 000001b to indicate that the

9:4

MLW

TUSB73X0 only supports a 1x PCI Express link.

Maximum Link Speed. This field is encoded 0010b to indicate that the

3:0

MLS

TUSB73X0 supports link speeds of 5 Gb/s and 2.5 Gb/s.

4.43 Link Control Register

The Link Control Register indicates is used to control link specific behavior.

PCI register offset: 80h

Default value: 0000h

Table 4-61. PCI Register 80h

Bit

No.

Reset

State

Table 4-62. Link Control Register Description

Bit

Field Name

Access

Description

15:9

RSVD

Reserved. Returns zeros when read.

EN_CPM

Enable Clock Power Management.

Extended Synch.

Common Clock Configuration. This bit is set when a common clock is

provided to both ends of the PCI Express link. This bit is also used to

select the L0s exit latency and L1 exit latency.

0 – Reference clock is asynchronous (L0s exit latency and L1 exit

CCC

latency based on the L0s_EXIT_LAT_ASYNC and

L1_EXIT_LAT_ASYNC fields in the General Control Register 0)

1 – Reference clock is synchronous (L0s exit latency and L1 exit latency

based on the L0s_EXIT_LAT_COMMON and L1_EXIT_LAT_COMMON

fields in the General Control Register 0)

Retrain Link. This bit has no function and is read only zero.

Link Disable. This bit has no function and is read only zero.

RCB

Read Completion Boundary.

RSVD

Reserved. Returns zero when read.

CLASSIC PCI CONFIGURATION SPACE

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