TUSB7320 datasheet(74/115 Pages) TI1

74 / 115 page

TUSB7320, TUSB7340

SLLSE76J – MARCH 2011 – REVISED MAY 2012

www.ti.com

xHCI MEMORY MAPPED REGISTER SPACE

6.1

The xHCI Register Map

The TUSB73X0 includes xHCI registers in memory mapped register space. These registers are accessible

via the address programmed into the Base Address Register 0/1.

All bits marked with a ‘*’ are sticky bits and are only reset by a Global Reset (GRST#).

Table 6-1. xHCI Register Map

Offset

Host Controller Capability Registers

000h-01Fh

Host Controller Operational Registers

020h-49Fh

Runtime Registers

4A0h-5BFh

Doorbell Registers

5C0h-6C3h

Reserved

6C4-9BFh

xHCI Extended Capabilities Registers

9C0h-9EBh

Reserved

9ECh-FFFFFh

6.2

Host Controller Capability Registers

These registers specify the limits and capabilities of the TUSB7340. The offset in then table is from the

address programmed into the Base Address Register 0.

Table 6-2. Host Controller Capability Register Map

Offset

HC Interface Version

Reserved

Capability Length

00h

HC Structural Parameters 1

04h

HC Structural Parameters 2

08h

HC Structural Parameters 3

0Ch

HC Capability Parameters

10h

Doorbell Offset

14h

Runtime Register Space Offset

18h

Reserved

1Ch-1Fh

6.2.1

Capability Registers Length

This read only register returns 20h when read to indicate that the beginning of the Operational Register

Space is at an offset of 20h from the address programmed into the Base Address Register 0.

BAR0 register offset: 00h

Default value: 0020h

Table 6-3. HC Capability Register 00h

Bit

No.

Reset

State

xHCI MEMORY MAPPED REGISTER SPACE

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