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TUSB7320 Datasheet(PDF) 37 Page - Texas Instruments |
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TUSB7320 Datasheet(HTML) 37 Page - Texas Instruments |
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37 / 115 page  TUSB7320, TUSB7340 www.ti.com SLLSE76J – MARCH 2011 – REVISED MAY 2012 4.18 Interrupt Line Register This read/write register is programmed by the system and indicates to the software which interrupt line the TUSB73X0 has been assigned. The default value of this register is FFh, indicating that an interrupt line has not yet been assigned to the function PCI register offset: 3Ch Register type:Read-only Default value: FFh Table 4-25. PCI Register 3Ch Bit No. 7 6 5 4 3 2 1 0 Reset State 1 1 1 1 1 1 1 1 4.19 Interrupt Pin Register The Interrupt Pin register is read-only 01h indicating that the TUSB73X0 uses INTA. PCI register offset: 3Dh Register type:Read-only Default value: 01h Table 4-26. PCI Register 3Dh Bit No. 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 1 4.20 Min Grant Register This read-only register has no meaningful context for a PCI Express device and returns zeros when read. PCI register offset: 3Eh Register type:Read-only Default value: 00h Table 4-27. PCI Register 3Eh Bit No. 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 4.21 Max Latency Register This read-only register has no meaningful context for a PCI Express device and returns zeros when read. PCI register offset: 3Fh Register type:Read-only Default value: 00h Table 4-28. PCI Register 3Fh Bit No. 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 Copyright © 2011–2012, Texas Instruments Incorporated CLASSIC PCI CONFIGURATION SPACE 37 Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 |
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