TUSB7320 datasheet(71/115 Pages) TI1

71 / 115 page

TUSB7320, TUSB7340

www.ti.com

SLLSE76J – MARCH 2011 – REVISED MAY 2012

5.9

Advanced Error Capabilities and control Register

The Advanced Error Capabilities and Control Register allows the system to monitor and control the

advanced error reporting capabilities.

PCI Express Extended Register Offset: 118h

Default value: 0000 0050h

Table 5-14. PCI Express Extended Register 118h

Bit

No.

Reset

State

Bit

No.

Reset

State

Table 5-15. Bit Descriptions – Advanced Error Capabilities and Control Register(1)

Bit

Field Name

Access

Description

31:9

RSVD

Reserved. Returns zeros when read.

Extended CRC Check Enable.

8†

ECRC_CHK_EN †

0 – Extended CRC checking is Disabled

1 – Extended CRC checking is Enabled

Extended CRC Check Capable. This read-only bit returns a value of ‘1’

ECRC_CHK_CAPABLE

indicating that the TUSB73X0 is capable of checking extended CRC

information.

Extended CRC Generation Enable.

6†

ECRC_GEN_EN †

0 – Extended CRC generation is Disabled

1 – Extended CRC generation is Enabled

Extended CRC Generation Capable. This read-only bit returns a value of

ECRC_GEN_CAPABLE

‘1’ indicating that the TUSB73X0 is capable of generating extended CRC

information.

First Error Pointer. This five bit value reflects the bit position within the

4:0†

FIRST_ERR †

Uncorrectable Error Status Register corresponding to the class of the

first error condition that was detected.

(1)

Bits marked with † are reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset

PCI EXPRESS EXTENDED CONFIGURATION SPACE

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