TUSB7320 datasheet(30/115 Pages) TI1

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TUSB7320, TUSB7340

SLLSE76J – MARCH 2011 – REVISED MAY 2012

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4.4

Command Register

The Command register provides control over the TUSB73X0 interface to the PCIe interface

PCI register offset: 04h

Default value: 0000h

Table 4-4. PCI Register 04h

Bit

No.

Reset

State

Table 4-5. Bit Command Register Description

Bit

Field Name

Access

Description

15:11

RSVD

Reserved. Returns zeros when read.

INT_DISABLE

INTx# Disable. This bit enables device specific interrupts.

Fast back-to-back enable. The host controller does not generate fast back-to-

FBB_ENB

back transactions; therefore, this bit returns 0 when read.

SERR enable bit. When this bit is set, the host controller can signal fatal and

nonfatal errors on the PCI Express interface on behalf of SERR assertions

SERR_ENB

detected on the PCI bus.

0 = Disable the reporting of nonfatal errors and fatal errors (default)

1 = Enable the reporting of nonfatal errors and fatal errors

Address/data stepping control. The host controller does not support

STEP_ENB

address/data stepping, and this bit is hardwired to 0b.

Controls the setting of bit 8 (DATAPAR) in the status register (offset 06h, see

Section 4.5) in response to a received poisoned TLP from PCI Express. A

received poisoned TLP is forwarded with bad parity to conventional PCI

PERR_ENB

regardless of the setting of this bit.

0 = Disables the setting of the master data parity error bit (default)

1 = Enables the setting of the master data parity error bit

VGA palette snoop enable. The host controller does not support VGA palette

VGA_ENB

snooping; therefore, this bit returns 0b when read.

Memory write and invalidate enable. The host controller does not support

MWI_ENB

memory write and invalidate enable; therefore, this bit returns 0b when read.

Special cycle enable. This host controller does not respond to special cycle

SPECIAL

transactions; therefore, this bit returns 0 when read.

Bus master enable. When this bit is set, the host controller is enabled to initiate

transactions on the PCI Express interface.

0 = PCI Express interface cannot initiate transactions. The host controller must

disable the response to memory and I/O transactions on the PCI interface

MASTER_ENB

(default).

1 = PCI Express interface can initiate transactions. The host controller can

forward memory and I/O transactions from PCI secondary interface to the PCI

Express interface.

Memory space enable. Setting this bit enables the host controller to respond to

memory transactions on the PCI Express interface.

0 = PCI Express receiver cannot process downstream memory transactions

MEMORY_ENB

and must respond with an unsupported request (default)

1 = PCI Express receiver can process downstream memory transactions. The

host controller can forward memory transactions to the PCI interface.

I/O space enable. Setting this bit enables the host controller to respond to I/O

transactions on the PCI Express interface.

0 = PCI Express receiver cannot process downstream I/O transactions and

IO_ENB

must respond with an unsupported request (default)

1 = PCI Express receiver can process downstream I/O transactions. The host

controller can forward I/O transactions to the PCI interface.

CLASSIC PCI CONFIGURATION SPACE

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