TUSB7320 datasheet(42/115 Pages) TI1

42 / 115 page

TUSB7320, TUSB7340

SLLSE76J – MARCH 2011 – REVISED MAY 2012

www.ti.com

4.32 MSI Upper Message Address Register

This register contains the upper 32 bits of the address that a MSI message is written to when an interrupt

is to be signaled. If this register is 0000 0000h, 32-bit addressing is used; otherwise, 64-bit addressing is

used.

PCI register offset: 50h

Default value: 0000 0000h

Table 4-43. PCI Register 4Ch

Bit

No.

Reset

State

Bit

No.

Reset

State

4.33 MSI Message Data Register

This 16-bit register contains the data that software programmed the device to send when it sends a MSI

message.

PCI register offset: 54h

Default value: 0000h

Table 4-44. PCI Register 54h

Bit

No.

Reset

State

Table 4-45. MSI Message Data Register Description

Bit

Field Name

Access

Description

System Specific Message. This field contains the portion of the message

15:4

MSG

that the TUSB73X0 can never modify.

Message Number. This portion of the message field may be modified to

contain the message number if multiple messages are enabled. The

number of bits that are modifiable depends on the number of messages

enabled in the Message Control Register.

1 Message – No message data bits can be modified

3:0

MSG_NUM

2 messages – Bit 0 can be modified

4 messages – Bits 0:1 can be modified

8 messages – Bits 0:2 can be modified

16 messages – Bits 0:3 can be modified

32 messages – Bits 0:4 can be modified

CLASSIC PCI CONFIGURATION SPACE

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