TUSB7320 datasheet(85/115 Pages) TI1

85 / 115 page

TUSB7320, TUSB7340

www.ti.com

SLLSE76J – MARCH 2011 – REVISED MAY 2012

Table 6-32. Port Status and Control Register Description (continued)

WDE *

Wake on Disconnect Enable.

WCE *

Wake on Connect Enable.

RSVD

Reserved. Return zero when read.

Port Config Error Change. This field is only valid for USB 3.0 protocol

CEC *

rc or r

ports. For USB 2.0 protocol ports, this bit is reserved.

PLC *

Port Link State Change.

PRC *

Port Reset Change.

OCC *

Over-current Change.

Warm Port Reset Change. This field is only valid for USB 3.0 protocol

WRC *

rc or r

ports. For USB 2.0 protocol ports, this bit is reserved.

PEC *

Port Enabled/Disabled Change.

CSC *

Connect Status Change.

LWS

Port Link State Write Strobe. This bit returns a zero when read.

Port Indicator Control. Since the TUSB73X0 does not support port

15:14

PIC *

indicators, this field has no effect.

13:10

PORT_SPEED *

Port Speed

PP *

Port Power.

8:5

PLS *

Port Link State

PR *

Port Reset.

OCA

Over-current Active.

RSVD

Reserved. Returns zero when read.

PED *

Port Enabled/Disabled.

CCS *

Current Connect Status.

6.3.10 Port PM Status and Control Register (USB 3.0 Ports)

The TUSB73X0 implements a Port PM Status and Control Register for each port that is implemented. The

number of Port PM Status and Control Registers is the same as the value in the MAX_PORTS field in the

Host Controller Structural Parameters 1 Register (see Section 6.2.3).

Operational Base register offset:404h + (10h*(n-1))), where n = Port Number

Default value: 0000 0000h

Table 6-33. HC Operational Register (Operational Base + 404h + (10h*(n-1))), where n = Port Number

Bit

No.

Reset

State

Bit

No.

Reset

State

Table 6-34. Port PM Status and Control Register (USB 3.0) Description

Bit

Field Name

Access

Description

31:17

RSVD

Reserved. Returns zeros when read.

FLA

Force Link PM Accept.

15:8

U2_TIMEOUT*

U2 Timeout.

7:0

U1_TIMEOUT*

U1 Timeout.

xHCI MEMORY MAPPED REGISTER SPACE

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