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TUSB7320 Datasheet(PDF) 47 Page - Texas Instruments |
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TUSB7320 Datasheet(HTML) 47 Page - Texas Instruments |
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47 / 115 page  TUSB7320, TUSB7340 www.ti.com SLLSE76J – MARCH 2011 – REVISED MAY 2012 4.41 Device Status Register The Device Status Register controls PCI Express device specific parameters. PCI register offset: 7Ah Register type:Read Only, Clear by a Write of One, Hardware Update Default value: 00x0h Table 4-57. PCI Register 7Ah Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 No. Reset 0 0 0 0 0 0 0 0 0 0 0 x 0 0 0 0 State Table 4-58. Device Status Register Description Bit Field Name Access Description 15:6 RSVD r Reserved. Return zeros when read. 5 PEND ru Transaction Pending. AUX Power Detected. This bit indicates that AUX power is present. 0 – No AUX power detected. (AUX_DET pin is ‘0’) 4 APD ru 1 – AUX power detected. (AUX_DET pin is ‘1’) This bit is set based upon the state of the AUX_DET pin. 3 URD rcu Unsupported Request Detected. 2 FED rcu Fatal Error Detected. 1 NFED rcu Non-Fatal Error Detected. 0 CED rcu Correctable Error Detected. 4.42 Link Capabilities Register The Link Capabilities Register indicates the link specific capabilities of the TUSB73X0. PCI register offset: 7Ch Register type:Read-only Default value: 0007 xC12h Table 4-59. PCI Register 7Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 No. Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 State Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 No. Reset 0 x x 1 1 1 0 0 0 0 0 1 0 0 1 0 State Table 4-60. Link Capabilities Register Description Bit Field Name Access Description Port Number. This field indicates port number for the PCI Express link. 31:24 PORT_NUM r This field is read only 00h indicating that the Link is associated with port zero. 23:19 RSVD r Reserved. Returns zeros when read. Copyright © 2011–2012, Texas Instruments Incorporated CLASSIC PCI CONFIGURATION SPACE 47 Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 |
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