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TUSB7320 Datasheet(PDF) 57 Page - Texas Instruments

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Part # TUSB7320
Description  USB 3.0 xHCI HOST CONTROLLER
PDF  115 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TUSB7320 Datasheet(HTML) 57 Page - Texas Instruments

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TUSB7320, TUSB7340
www.ti.com
SLLSE76J – MARCH 2011 – REVISED MAY 2012
4.60 Subsystem Access Register
This register is a read/write register and the contents of this register are aliased to the Subsystem Vendor
ID and Subsystem ID Registers at PCI Offsets 2Ch and 2Eh. This register is reset by a PCI Express reset
(PERST#), a GRST#, or the internally-generated power-on reset.
PCI register offset: D0h
Register type:Read/Write
Default value: 0000 0000h
Table 4-91. PCI Register D0h
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
No.
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
State
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
No.
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
State
Table 4-92. Subsystem Access Register Description
Bit
Field Name
Access
Description
Subsystem ID. The value written to this field is aliased to the Subsystem
31:16†
SubsystemID†
rw
ID Register at PCI Offset 2Eh.
Subsystem Vendor ID. The value written to this field is aliased to the
15:0†
SubsystemVendorID†
rw
Subsystem Vendor ID Register at PCI Offset 2Ch.
4.61 General Control 0 Register
This register is a read/write register is used to control various functions of the TUSB73X0. This register is
reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset.
PCI register offset: D4h
Register type:Read/Write
Default value: 0000 0D9Bh
Table 4-93. PCI Register D4h
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
No.
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
State
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
No.
Reset
0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
1
State
Copyright © 2011–2012, Texas Instruments Incorporated
CLASSIC PCI CONFIGURATION SPACE
57
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Product Folder Link(s): TUSB7320 TUSB7340



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