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TUSB7320 Datasheet(PDF) 40 Page - Texas Instruments |
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TUSB7320 Datasheet(HTML) 40 Page - Texas Instruments |
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40 / 115 page  TUSB7320, TUSB7340 SLLSE76J – MARCH 2011 – REVISED MAY 2012 www.ti.com 4.27 Power Management Data Register This read-only register is not applicable to the TUSB73X0 and returns 00h when read. PCI register offset: 47h Register type:Read-only Default value: 00h Table 4-36. PCI Register 47h Bit No. 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 4.28 MSI Capability ID Register This read-only register identifies the linked list item as the register for Message Signaled Interrupts Capabilities. The register returns 05h when read. PCI register offset: 48h Register type:Read-only Default value: 05h Table 4-37. PCI Register 48h Bit No. 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 1 0 1 4.29 Next Item Pointer Register The contents of this read-only register indicate the next item in the linked list of capabilities for the TUSB73X0. This register reads 70h pointing to the PCI Express Capability registers. PCI register offset: 49h Register type:Read-only Default value: 70h Table 4-38. PCI Register 49h Bit No. 7 6 5 4 3 2 1 0 Reset State 0 1 1 1 0 0 0 0 4.30 MSI Message Control Register The register is used to control the sending of MSI messages. PCI register offset: 4Ah Register type:Read/Write, Read-only Default value: 0086h Table 4-39. PCI Register 4Ah Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 No. Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 State 40 CLASSIC PCI CONFIGURATION SPACE Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 |
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