TLK10232 datasheet(33/102 Pages) TI

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TLK10232

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SLLSEE1 – MAY 2013

The latency measurement does not include the low speed side transmit SERDES contribution as well as

part of the channel synchronization block. The latency introduced by those two is up to (18 + 10) x N high

speed side unit intervals (UIs), where N = 2, 4 is the multiplex factor. The latency measurement also

doesn’t account for the low speed side receive SERDES contribution which is estimated to be up to 20 x N

high speed side UIs.

The latency measurement accuracy in all cases is equal to plus or minus one latency measurement clock

period. The measurement clock can be divided down if a longer duration measurement is required, in

which case the accuracy of the measurement is accordingly reduced. The high speed latency

measurement clock is divided by either 1, 2, 4, or 8 via register settings. The measurement clock used is

always selected by the channel under test. The high speed latency measurement clock may only be used

when operating at one of the serial rates specified in the CPRI/OBSAI specifications. It is also possible to

run the latency measurement function off of the recovered byte clock for the channel under test (giving a

latency measurement clock frequency equal to the serial bit rate divided by 20).

The accuracy for the standard based CPRI/OBSAI application rates is shown in Table 7-1, and assumes

the latency measurement clock is not divided down per user selection (division is required to measure a

duration greater than 682us). For each division of 2 in the measurement clock, the accuracy is also

reduced by a factor of two.

Table 7-1. CPRI/OBSAI Latency Measurement Function Accuracy (Undivided

Measurement Clock)

LATENCY CLOCK

LINE RATE

ACCURACY

RATE

FREQUENCY

(Gbps)

(± ns)

(GHz)

1.2288

Eighth

1.2288

0.8138

1.536

Quarter

0.768

1.302

2.4576

Quarter

1.2288

0.8138

3.072

Half

0.768

1.302

3.84

Half

0.96

1.0417

4.9152

Half

1.2288

0.8138

6.144

Full

0.768

1.302

7.68

Full

0.96

1.0417

9.8304

Full

1.2288

0.8138

7.5

Power Down Mode

The TLK10232 can be put in power down either through device input pins or through MDIO control

•

PDTRXA_N: Active low, powers down channel A.

•

PDTRXB_N: Active low, powers down channel B.

ADDITIONAL FEATURES

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