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TLK10232 Datasheet(PDF) 23 Page - Texas Instruments |
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TLK10232 Datasheet(HTML) 23 Page - Texas Instruments |
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23 / 102 page  TLK10232 LAS Lane Alignment Slave Lane Align 10B à8B 10B à8B 10B à8B 10B à8B 10B ß 8B 10B ß 8B 10B ß 8B 10B ß 8B LAM Lane Alignment Master Link Partner Device LAS Lane Alignment Slave Low Speed Side SERDES Channel A (4 RX/ 4 TX) CH SYNC Lane Align LAM Lane Alignment Master LS _OK _ OUT _A LS _OK _IN_A OUTA[3:0]P/N INA[3:0]P/N 8B à 8B à 8B à 8B à 10B 10B 10B 10B 8B ß 8B ß 8B ß 8B ß 10B 10B 10B 10B Low Speed Side SERDES Channel A (4 RX/ 4 TX) CH SYNC CH SYNC CH SYNC CH SYNC CH SYNC CH SYNC CH SYNC TLK10232 www.ti.com SLLSEE1 – MAY 2013 Figure 5-2. Block Diagram of the Lane Alignment Scheme 5.6 Lane Alignment Components • Lane Alignment Master (LAM) – Responsible for generating proprietary LS lane alignment initialization pattern – Resides in the TLK10232 receive path (one instance per channel) • Responsible for bringing up LS receive link for the data sent from the TLK10232 to a link partner device • Monitors the LS_OK_IN pins for “Link Status OK” signals sent from the Lane Alignment Slave (LAS) of the link partner device – Resides in the link partner device (one instance per channel) • Responsible for bringing up LS transmit link for the data sent from the link partner device to the TLK10232 • Monitors the “Link Status OK” signals sent from the LS_OK_OUT pins of the Lane Alignment Slave (LAS) of the TLK10232 • Lane Alignment Slave (LAS) – Responsible for monitoring the LS lane alignment initialization pattern – Performs channel synchronization per lane (2 or 4 lanes) through byte rotation – Performs lane alignment and realignment of bytes across lanes – Resides in the TLK10232 transmit path (one instance per channel) • Generates the “Link Status OK” signal for the LAM on the link partner device – Resides in the link partner device (one instance per channel) • Generates the “Link Status OK” signal for the LAM on the TLK10232 device. Reference code from Texas Instruments is available for the LAM and LAS modules for easy integration into FPGAs. 5.7 Lane Alignment Operation During lane alignment, the LAM sends a repeating pattern of 49 characters (control + data) simultaneously across all enabled LS lanes. These simultaneous streams are then encoded by 8B/10B encoders in parallel. The proprietary lane alignment pattern consists of the following characters: /K28.5/ (CTL=1, Data=0xBC) Copyright © 2013, Texas Instruments Incorporated GENERAL PURPOSE (10G) SERDES MODE FUNCTIONAL 23 DESCRIPTION Submit Documentation Feedback Product Folder Links: TLK10232 |
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