TLK10232 datasheet(7/102 Pages) TI

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TLK10232

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SLLSEE1 – MAY 2013

Table 2-1. Pin Description - Signal Pins (continued)

TERMINAL

DIRECTION

TYPE

DESCRIPTION

SIGNAL

BGA

SUPPLY

Channel B Receive Loss Of Signal (LOS) Indicator.

LOSB=0: Signal detected.

LOSB=1: Loss of signal.

Loss of signal detection is based on the input signal level.

When HSRXBP/N has a differential input signal swing of

≤75 mVpp, LOSB will be asserted

(if enabled). If the input signal is greater than 150 mVp-p, LOS will be deasserted. Outside

Output

of these ranges, the LOS indication is undefined.

LOSB

LVCMOS 1.5V/1.8V

Other functions can be observed on LOSB real-time, configured via MDIO

VDDO1 40

Ω Driver

During device reset (RESET_N asserted low) this pin is driven low. During pin based

power down (PDTRXB_N asserted low), this pin is floating. During register based power

down, this pin is floating.

It is highly recommended that LOSB be brought to easily accessible point on the

application board (header), in the event that debug is required.

Channel B Receive Lane Alignment Status Indicator. Lane alignment status signal

Input

received from a Lane Alignment Slave on the link partner device. Valid in 10G General

LS_OK_IN_B

LVCMOS 1.5V/1.8V

Purpose Serdes Mode.

VDDO0

LS_OK_IN_B=0: Channel B Receive lanes not aligned.

LS_OK_IN_B=1: Channel B Receive lanes aligned

Channel B Transmit Lane Alignment Status Indicator. Lane alignment status signal

Output

sent to a Lane Alignment Master on the link partner device. Valid in 10G General Purpose

LS_OK_OUT_B

LVCMOS 1.5V/1.8V

Serdes Mode.

VDDO0 40

Ω Driver

LS_OK_OUT_B=0: Channel B Transmit lanes not aligned.

LS_OK_OUT_B=1: Channel B Transmit lanes aligned.

Input

Transceiver Power Down. When this pin is held low (asserted), Channel B is placed in

PDTRXB_N

LVCMOS

power down mode. When deasserted, Channel B operates normally. After deassertion, a

1.5V/1.8V VDDO1

software data path reset should be issued through the MDIO interface.

REFERENCE CLOCKS, OUTPUT CLOCKS, AND CONTROL AND MONITORING SIGNALS

Reference Clock Input Zero. This differential input is a clock signal used as a reference

Input

M10

to channels A or B. The reference clock selection is done through MDIO. This input signal

REFCLK0P/N

LVDS/ LVPECL

M11

must be AC coupled. If unused, REFCLK0P/N should be pulled down to GND through a

DVDD

shared 100

Ω resistor.

Reference Clock Input One. This differential input is a clock signal used as a reference

Input

to channels A or B. The reference clock selection is done through MDIO. This input signal

REFCLK1P/N

LVDS/ LVPECL

K10

must be AC coupled. If unused, REFCLK1P/N should be pulled down to GND through a

DVDD

shared 100

Ω resistor.

Channel A/B Output Clock. By default, these outputs are enabled and output the high

speed side Channel A recovered byte clock (high speed line rate divided by 16 or 20).

Optionally, they can be configured to output the VCO clock divided by 2. (Note: for full

rates, VCO/2 pre-divided clocks will be equivalent to the line rate divided by 8; for sub-

Output

CLKOUTAP/N

C9/C10

rates, VCO/2 pre-divided clocks will be equivalent to the line rate divided by 4).

CML

CLKOUTBP/N

A9/A10

DVDD

These CML outputs must be AC coupled.

During device reset (RESET_N asserted low), pin-based power down (PDTRXA_N and

PDTRXB_N asserted low), or register-based power down, these pins are floating.

Enable PRBS: When this pin is asserted high, the internal PRBS generator and verifier

circuits are enabled on both transmit and receive data paths on high speed and low speed

Input

sides of both channels.

PRBSEN

LVCMOS 1.5V/1.8V

VDDO0

The PRBS 27-1 pattern is selected by default, and can be changed through MDIO.

Receive PRBS Error Free (Pass) Indicator.

When PRBS test is enabled (PRBSEN=1):

PRBS_PASS=1 indicates that PRBS pattern reception is error free.

PRBS_PASS=0 indicates that a PRBS error is detected. The channel, high speed or low

speed side, and lane (for low speed side) that this signal refers to is chosen through

MDIO.

Output

PRBS_PASS

LVCMOS 1.5V/1.8V

During device reset (RESET_N asserted low) this pin is driven high.

VDDO1 40

Ω Driver

During pin based power down (PDTRXA_N and PDTRXB_N asserted low), this pin is

floating.

During register based power down, this pin is floating.

It is highly recommended that PRBS_PASS be brought to easily accessible point on the

application board (header), in the event that debug is required.

MDIO Select. Used to select Clause 22 (=1) or Clause 45 (=0) operation. Note that

Input

selecting clause 22 will impact mode availability. See MODE_SEL.

LVCMOS 1.5V/1.8V

VDDO[1:0]

A hard or soft reset must be applied after a change of state occurs on this input signal.

Input LVCMOS

Device Operating Mode Select.

MODE_SEL

H10

1.5V/1.8V VDDO[1:0]

Used together with ST pin to select device operating mode. See Table 2-3 for details.

Physical Characteristics

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