TLK10232 datasheet(64/102 Pages) TI

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TLK10232

SLLSEE1 – MAY 2013

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Table 8-55. TRIGGER_LOAD_CONTROL

Device Address: 0x1E SPACER Register Address:0x8100 SPACER Default: 0x0000

Bit(s)

Name

Description

Access

15:11

RESERVED

For TI use only. Always reads 0.

10:3

RESERVED

For TI use only. (Default 8'b00000000)

Valid only when DEFAULT_TX_TRIGGER_EN is HIGH

DEFAULT_TX_LOAD_TRI

1 = Trigger loading default HS TX setting values

GGER

0 = Normal operation (Default 1'b0)

(RXG)

This bit needs to be written HIGH and then LOW to load the HS Tx default values.

Applicable when link training is enabled.

1:0

RESERVED

For TI use only. (Default 2'b00)

Table 8-56. TRIGGER_EN_CONTROL

Device Address: 0x1E SPACER Register Address:0x8101 SPACER Default: 0x0000

Bit(s)

Name

Description

Access

15:11

RESERVED

For TI use only. Always reads 0.

10:3

RESERVED

For TI use only. (Default 8'b00000000)

DEFAULT_TX_TRIGGER_

1 = Enable loading of Tx default values through DEFAULT_TX_LOAD_TRIGGER

0 = Normal operation (Default 1'b0)

(RXG)

1:0

RESERVED

For TI use only. (Default 2'b00)

8.2

PMA/PMD Registers

The registers below can be accessed only in Clause 45 mode and with device address field set to 0x01

(DA[4:0] = 5’b00001).

NOTE: Link training registers can also be accessed in Clause 22 mode using indirect address method and

in Clause 45 mode with device address field set to 0x1E (DA[4:0] = 5’b11110). Link training registers are

also applicable in 10G and 1GKX modes.

Table 8-57. PMA_CONTROL_1

Device Address: 0x01 SPACER Register Address:0x0000 SPACER Default: 0x0000

Bit(s)

Name

Description

Access

1 = Global reset. Resets datapath and MDIO registers of all channels. Equivalent to

RESET

asserting RESET_N.

RW/SC

(RX)

0 = Normal operation (Default 1’b0)

14:12

RESERVED

For TI use only. Always reads 0.

POWERDOWN

1 = Enable power down mode

(RX)

0 = Normal operation (Default 1’b0)

10:1

RESERVED

For TI use only. Always reads 0.

1 = Enables loopback on HS side. LS data traverses through entire Tx datapath

LOOPBACK

excluding HS serdes and will be available at LS output side

(RX)

0 = Normal operation (Default 1’b0)

Table 8-58. PMA_STATUS_1

Device Address: 0x01 SPACER Register Address:0x0001 SPACER Default: 0x0002

Bit(s)

Name

Description

Access

FAULT

1 = Fault condition detected on either Tx or Rx side

(RX)

0 = No fault condition detected

This bit is cleared after Register 01.0008 is read and no fault condition occurs after

01.0008 is read.

RX_LINK

1 = Receive link is up

RO/LL

(RX)

0 = Receive link is down

DEVICE REGISTERS

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