TLK10232 datasheet(11/102 Pages) TI

11 / 102 page

TLK10232

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SLLSEE1 – MAY 2013

3.2

10GBASE-KR Receive Data Path Overview

In the receive direction, the TLK10232 will take in 64B/66B-encoded serial 10GBASE-KR data on the

HSRX*P/N pins. This data is deserialized by a high speed SERDES, then input to a receive gearbox. After

the gearbox, the data is aligned to 66-bit frames, descrambled, 64B/66B decoded, and then input to the

receive CTC block. After CTC, the data is encoded by four 8B/10B encoders, and the resulting four 10-bit

parallel words are serialized by the low speed SERDES blocks. The four serial XAUI output lanes are

transmitted out the OUT*P/N pins.

3.3

Channel Synchronization Block

When parallel data is clocked into a parallel-to-serial converter, the byte boundary that was associated

with the parallel data is lost in the serialization of the data. When the serial data is received and converted

to parallel format again, a method is needed to be able to recognize the byte boundary again. Generally,

this is accomplished through the use of a synchronization pattern. This is a unique pattern of 1’s and 0’s

that either cannot occur as part of valid data or is a pattern that repeats at defined intervals. 8B/10B

encoding contains a character called the comma (b’0011111’ or b’1100000’) which is used by the comma

detect circuit to align the received serial data back to its original byte boundary. The TLK10232 channel

synchronization block detects the comma pattern found in the K28.5 character, generating a

synchronization signal aligning the data to their 10-bit boundaries for decoding. It is important to note that

the comma can be either a (b’0011111’) or the inverse (b’1100000’) depending on the running disparity.

The TLK10232 decoder will detect both patterns.

The TLK10232 performs channel synchronization per lane as shown in the flowchart of Figure 3-2.

10GBASE-KR MODE FUNCTIONAL DESCRIPTION

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