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TLK10232 Datasheet(PDF) 71 Page - Texas Instruments |
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TLK10232 Datasheet(HTML) 71 Page - Texas Instruments |
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71 / 102 page  TLK10232 www.ti.com SLLSEE1 – MAY 2013 Table 8-81. KR_VS_FIFO_CONTROL_1 (continued) Device Address: 0x01 SPACER Register Address: 0x8001 SPACER Default: 0xCC4C Bit(s) Name Description Access Tx CTC FIFO depth selection TX_FIFO_DEPTH[2:0] 1xx = 32 deep (Default 3’b100)011 = 24 deep 6:4 RW (R) 010 = 16 deep001 = 12 deep 000 = 8 deep (No CTC function) Water mark selection for receive CTC Works in conjunction with TX_FIFO_DEPTH_SEL setting (Default 2’b11) Depth-> 32 24 26 12/8 TX_CTC_WMK_SEL[1:0] 3:2 RW 11 High High High NA (R) 10 Mid-high Mid High 01 Mid Low Low 00 Low Low Low TX_Q_CNT_IPG 0 = Normal operation. (Default 1’b0) 1 RW (R) 1 = Sequence columns are counted as IPG. TX_CTC_Q_DROP_EN 0 = Normal operation. (Default 1’b0) 0 RW (R) 1 = Enable Q column drop in TX CTC. Table 8-82. KR_VS_TP_GEN_CONTROL Device Address: 0x01SPACER Register Address:0x8002SPACER Default: 0x0000 Bit(s) Name Description Access 15:6 RESERVED For TI use only. Always reads 0. RW XAUI based test pattern selection on LS side. See Test pattern procedures for more information. RX_TPG_HLM_TEST_SEL[1:0] 00 = High Frequency test pattern(Default 2’b00) 5:4 RW (R) 01 = Low Frequency test pattern 10 = Mixed Frequency test pattern 11 = Normal operation XAUI based test pattern selection on LS side. See Test pattern RX_TPG_CRPAT_TEST_EN procedures for more information. 3 RW (R) 0 = Normal operation. (Default 1’b0) 1 = Enables CRPAT test pattern generation XAUI based test pattern selection on LS side. See Test pattern RX_TPG_CJPAT_TEST_EN procedures for more information. 2 RW (R) 0 = Normal operation. (Default 1’b0) 1 = Enables CJPAT test pattern generation XAUI based test pattern selection on LS side. See Test pattern RX_TPG_10GFC_TEST_EN procedures for more information. 1 RW (R) 0 = Normal operation. (Default 1’b0) 1 = Enables 10 GFC CJPAT test pattern generation XAUI based test pattern selection on LS side. See Test pattern RX_TPG_HLM_TEST_EN procedures for more information. 0 RW (R) 0 = Normal operation. (Default 1’b0) 1 = Enables H/L/M test pattern generation Table 8-83. KR_VS_TP_VER_CONTROL Device Address: 0x01 SPACER Register Address:0x8003 SPACER Default: 0x0000 Bit(s) Name Description Access 15:14 RESERVED For TI use only. Always reads 0. RW XAUI based test pattern selection on LS side. See Test pattern procedures for more information. TX_TPV_HLM_TEST_SEL[1:0] 00 = High Frequency test pattern(Default 2’b00) 13:12 RW (R) 01 = Low Frequency test pattern 10 = Mixed Frequency test pattern 11 = Normal operation Copyright © 2013, Texas Instruments Incorporated DEVICE REGISTERS 71 Submit Documentation Feedback Product Folder Links: TLK10232 |
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