TLK10232 datasheet(18/102 Pages) TI

18 / 102 page

HSTXxP

HSTXxN

INx0N

INx0P

HSRXxP

HSRXxN

OUTx0N

OUTx0P

Test Pattern

Generation

Test Pattern

Verification

Test Pattern

Verification

Test Pattern

Generation

TLK10232

SLLSEE1 – MAY 2013

www.ti.com

1GBASE-KX MODE FUNCTIONAL DESCRIPTION

A simplified block diagram of the 1GBASE-KX data path is shown in Figure 4-1.

Figure 4-1. A Simplified One Channel Block Diagram of the 1GKX Data Path

4.1

Channel Sync Block

This block is used to align the deserialized signals to the proper 10-bit word boundaries. The Channel

Sync block generates a synchronization flag indicating incoming data is synchronized to the correct word

boundary. This module implements the synchronization state machine found in Figure 36-9 of the IEEE

802.3-2008 Standard. A synchronization status signal, latched low, is available to indicate synchronization

errors.

4.2

8b/10b Encoder and Decoder Blocks

As in the 10GBASE-KR operating mode, these blocks are used to convert between 10-bit (encoded) data

and 8-bit data words. They can be optionally bypassed. A code invalid signal, latched low, is available to

indicate 8b/10b encode and decode errors.

4.3

TX CTC

The transmit clock tolerance compensation (CTC) block acts as a FIFO with add and delete capabilities,

adding and deleting 2 cycles each time to support ±200ppm during IFG (no errors) between the read and

write clocks. This block implements a 12 deep asynchronous FIFO with a usable space 8 deep. It has two

separate pointer tracking systems. One determines when to delete or insert and another determines when

to reset. Inserts and deletes are only allowed during non-errored inter-frame gaps and occurs 2 cycles at a

time. It has an auto reset feature once collision occurs. If a collision occurs, the indication is latched high

until read by MDIO.

4.4

1GBASE-KX Line Rate, PLL Settings, and Reference Clock Selection

When the TLK10232 is configured to operate in the 1GBASE-KX mode, the available line rates, reference

clock frequencies, and corresponding PLL multipliers are summarized in Table 4-1.

1GBASE-KX MODE FUNCTIONAL DESCRIPTION

Submit Documentation Feedback

Product Folder Links: TLK10232

TLK10232 Datasheet(PDF) 18 Page - Texas Instruments

TLK10232 Datasheet(HTML) 18 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL