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TLK10232 Datasheet(PDF) 28 Page - Texas Instruments |
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TLK10232 Datasheet(HTML) 28 Page - Texas Instruments |
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28 / 102 page  TLK10232 SLLSEE1 – MAY 2013 www.ti.com The computed reference clock frequencies are shown in Table 5-6 along with the valid minimum and maximum frequency values. 3. Mark all the common frequencies that appear on both SERDES sides. Note and discard all those that fall outside the allowed range. In this example, the common frequencies are highlighted in Table 5-6. The highest and lowest computed reference clock frequencies must be discarded because they exceed the recommended range. 4. Select any of the remaining marked common reference clock frequencies. Higher reference clock frequencies are generally preferred. In this example, any of the following reference clock frequencies can be selected: 397.4MHz, 331.167MHz, 248.375MHz, 198.7MHz, 165.583MHz, 158.96MHz, and 132.467MHz Table 5-6. Reference Clock Frequency Selection Example LOW SPEED SIDE SERDES HIGH SPEED SIDE SERDES REFERENCE CLOCK FREQUENCY (MHz) REFERENCE CLOCK FREQUENCY (MHz) SERDES PLL SERDES PLL MULTIPLIER MULTIPLIER COMPUTED MIN MAX COMPUTED MIN MAX 4 496.750 250 425 4 496.750 375 425 5 397.400 200 425 5 397.400 300 425 6 331.167 166.667 416.667 6 331.167 250 416.667 8 248.375 125 312.5 8 248.375 187.5 312.5 10 198.700 122.88 250 10 198.700 150 250 12 165.583 122.88 208.333 12 165.583 125 208.333 12.5 158.960 122.88 200 12.5 158.960 153.6 200 15 132.467 122.88 166.667 15 132.467 122.88 166.667 20 99.350 122.88 125 20 99.350 122.88 125 5.9 General Purpose SERDES Mode Test Pattern Support The TLK10232 has the capability to generate and verify various test patterns for self-test and system diagnostic measurements. Most of the same test pattern support is available for 10G General Purpose Mode as for 10G-KR. (See Register 1E.000B for details). 5.10 General Purpose SERDES Mode Latency The latency through the TLK10232 in General Purpose SERDES mode is as shown in Figure 5-4. Note that the latency ranges shown indicate static rather than dynamic latency variance, i.e., the range of possible latencies when the serial link is initially established. During normal operation, the latency through the device is fixed. 28 GENERAL PURPOSE (10G) SERDES MODE FUNCTIONAL Copyright © 2013, Texas Instruments Incorporated DESCRIPTION Submit Documentation Feedback Product Folder Links: TLK10232 |
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