TLK10232 datasheet(10/102 Pages) TI

10 / 102 page

INx3N

HSTXxP

HSTXxN

INx3P

INx2N

INx2P

INx1N

INx1P

INx0N

INx0P

OUTx3N

HSRXxP

HSRXxN

OUTx3P

OUTx2N

OUTx2P

OUTx1N

OUTx1P

OUTx0N

OUTx0P

TLK10232

SLLSEE1 – MAY 2013

www.ti.com

10GBASE-KR MODE FUNCTIONAL DESCRIPTION

A simplified block diagram of the transmit and receive data paths in 10GBASE-KR mode is shown in

Figure 3-1. This section gives a high-level overview of how data moves through these paths, then gives a

more detailed description of each block’s functionality.

Figure 3-1. A Simplified One Channel KR Data Path Block Diagram

3.1

10GBASE-KR Transmit Data Path Overview

In 10GBASE-KR Mode, the TLK10232 takes in XAUI data on the four low speed input lanes. The serial

data in each lane is deserialized into 10-bit parallel data, then byte aligned (channel synchronized) based

on comma detection. The four XAUI lanes are then aligned with one another, and the aligned data is input

to four 8B/10B decoders. The decoded data is then input to the transmit clock tolerance compensation

(CTC) block which compensates for any frequency offsets between the incoming XAUI data and the local

reference clock. The CTC block then delivers the data to a 64B/66B encoder and a scrambler. The

resulting scrambled 10GBASE-KR data is then input to a transmit gearbox which in turn delivers it to the

high speed side SERDES for serialization and output through the HSTX*P/N pins.

10GBASE-KR MODE FUNCTIONAL DESCRIPTION

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TLK10232 Datasheet(PDF) 10 Page - Texas Instruments